Commit 0926d8d5 authored by Basheer Ahmed Muddebihal's avatar Basheer Ahmed Muddebihal Committed by Greg Kroah-Hartman
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fpga: dfl: Add DFHv1 Register Definitions 



This patch adds the definitions for DFHv1 header and related register
bitfields.

Signed-off-by: default avatarBasheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com>
Co-developed-by: default avatarMatthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: default avatarMatthew Gerlach <matthew.gerlach@linux.intel.com>
Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20230115151447.1353428-3-matthew.gerlach@linux.intel.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 46879f71

drivers/fpga/dfl.h

+32 −0
Original line number Diff line number Diff line
@@ -74,11 +74,43 @@ 
#define DFH_REVISION		GENMASK_ULL(15, 12)	/* Feature revision */

#define DFH_NEXT_HDR_OFST	GENMASK_ULL(39, 16)	/* Offset to next DFH */

#define DFH_EOL			BIT_ULL(40)		/* End of list */

#define DFH_VERSION		GENMASK_ULL(59, 52)	/* DFH version */

#define DFH_TYPE		GENMASK_ULL(63, 60)	/* Feature type */

#define DFH_TYPE_AFU		1

#define DFH_TYPE_PRIVATE	3

#define DFH_TYPE_FIU		4



/*

 * DFHv1 Register Offset definitons

 * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA

 * as common header registers

 */

#define DFHv1_CSR_ADDR		0x18  /* CSR Register start address */

#define DFHv1_CSR_SIZE_GRP	0x20  /* Size of Reg Block and Group/tag */

#define DFHv1_PARAM_HDR		0x28  /* Optional First Param header */



/*

 * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start),

 * 1'b1 = absolute (ARM or other non-PCIe use)

 */

#define DFHv1_CSR_ADDR_REL	BIT_ULL(0)



/* CSR Header Register Bit Definitions */

#define DFHv1_CSR_ADDR_MASK       GENMASK_ULL(63, 1)  /* 63:1 of CSR address */



/* CSR SIZE Goup Register Bit Definitions */

#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID	GENMASK_ULL(15, 0)	/* Enumeration instantiated IP */

#define DFHv1_CSR_SIZE_GRP_GROUPING_ID	GENMASK_ULL(30, 16)	/* Group Features/interfaces */

#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS	BIT_ULL(31)		/* Presence of Parameters */

#define DFHv1_CSR_SIZE_GRP_SIZE		GENMASK_ULL(63, 32)	/* Size of CSR Block in bytes */



/* PARAM Header Register Bit Definitions */

#define DFHv1_PARAM_HDR_ID		GENMASK_ULL(15, 0) /* Id of this Param  */

#define DFHv1_PARAM_HDR_VER		GENMASK_ULL(31, 16) /* Version Param */

#define DFHv1_PARAM_HDR_NEXT_OFFSET	GENMASK_ULL(63, 35) /* Offset of next Param */

#define DFHv1_PARAM_HDR_NEXT_EOP	BIT_ULL(32)

#define DFHv1_PARAM_DATA		0x08  /* Offset of Param data from Param header */



/* Next AFU Register Bitfield */

#define NEXT_AFU_NEXT_DFH_OFST	GENMASK_ULL(23, 0)	/* Offset to next AFU */