Commit 08f0cfbf authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.13-2021-05-13' of... 

Merge tag 'amd-drm-fixes-5.13-2021-05-13' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.13-2021-05-13:

amdgpu:
- Fixes for flexible array conversions
- Fix sysfs attribute init
- Harvesting fixes
- VCN CG/PG fixes for Picasso

radeon:
- Fixes for flexible array conversions
- Fix for flickering on Oland with multiple 4K displays

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210513163228.3963-1-alexander.deucher@amd.com
parents 1db7aa26 5c1efb5f

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -1006,6 +1006,7 @@ struct amdgpu_device { 
	struct amdgpu_df                df;



	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];

	uint32_t		        harvest_ip_mask;

	int				num_ip_blocks;

	struct mutex	mn_lock;

	DECLARE_HASHTABLE(mn_hash, 7);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+14 −1
Original line number Diff line number Diff line
@@ -1683,6 +1683,19 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 
	if (!ip_block_version)

		return -EINVAL;



	switch (ip_block_version->type) {

	case AMD_IP_BLOCK_TYPE_VCN:

		if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)

			return 0;

		break;

	case AMD_IP_BLOCK_TYPE_JPEG:

		if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)

			return 0;

		break;

	default:

		break;

	}



	DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,

		  ip_block_version->funcs->name);
@@ -3111,7 +3124,6 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) 
	return amdgpu_device_asic_has_dc_support(adev->asic_type);

}





static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)

{

	struct amdgpu_device *adev =
@@ -3276,6 +3288,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	adev->vm_manager.vm_pte_funcs = NULL;

	adev->vm_manager.vm_pte_num_scheds = 0;

	adev->gmc.gmc_funcs = NULL;

	adev->harvest_ip_mask = 0x0;

	adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);

	bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+28 −0
Original line number Diff line number Diff line
@@ -373,6 +373,34 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, 
	return -EINVAL;

}



void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)

{

	struct binary_header *bhdr;

	struct harvest_table *harvest_info;

	int i;



	bhdr = (struct binary_header *)adev->mman.discovery_bin;

	harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +

			le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));



	for (i = 0; i < 32; i++) {

		if (le32_to_cpu(harvest_info->list[i].hw_id) == 0)

			break;



		switch (le32_to_cpu(harvest_info->list[i].hw_id)) {

		case VCN_HWID:

			adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;

			adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;

			break;

		case DMU_HWID:

			adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;

			break;

		default:

			break;

		}

	}

}



int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)

{

	struct binary_header *bhdr;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 


void amdgpu_discovery_fini(struct amdgpu_device *adev);

int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);

void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);

int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,

                                    int *major, int *minor, int *revision);

int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/nv.c

+23 −15
Original line number Diff line number Diff line
@@ -623,6 +623,16 @@ static const struct amdgpu_ip_block_version nv_common_ip_block = 
	.funcs = &nv_common_ip_funcs,

};



static bool nv_is_headless_sku(struct pci_dev *pdev)

{

	if ((pdev->device == 0x731E &&

	    (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||

	    (pdev->device == 0x7340 && pdev->revision == 0xC9)  ||

	    (pdev->device == 0x7360 && pdev->revision == 0xC7))

		return true;

	return false;

}



static int nv_reg_base_init(struct amdgpu_device *adev)

{

	int r;
@@ -635,6 +645,12 @@ static int nv_reg_base_init(struct amdgpu_device *adev) 
			goto legacy_init;

		}



		amdgpu_discovery_harvest_ip(adev);

		if (nv_is_headless_sku(adev->pdev)) {

			adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;

			adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;

		}



		return 0;

	}
@@ -671,16 +687,6 @@ void nv_set_virt_ops(struct amdgpu_device *adev) 
	adev->virt.ops = &xgpu_nv_virt_ops;

}



static bool nv_is_headless_sku(struct pci_dev *pdev)

{

	if ((pdev->device == 0x731E &&

	    (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||

	    (pdev->device == 0x7340 && pdev->revision == 0xC9)  ||

	    (pdev->device == 0x7360 && pdev->revision == 0xC7))

		return true;

	return false;

}



int nv_set_ip_blocks(struct amdgpu_device *adev)

{

	int r;
@@ -728,7 +734,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (!nv_is_headless_sku(adev->pdev))

		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);

		amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);

		if (adev->enable_mes)
@@ -752,7 +757,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&

		    !amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		if (!nv_is_headless_sku(adev->pdev))

		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);

		if (!amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
@@ -777,7 +781,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);

		if (!amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);



		if (adev->enable_mes)

			amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);

		break;
@@ -1149,6 +1152,11 @@ static int nv_common_early_init(void *handle) 
		return -EINVAL;

	}



	if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)

		adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |

				    AMD_PG_SUPPORT_VCN_DPG |

				    AMD_PG_SUPPORT_JPEG);



	if (amdgpu_sriov_vf(adev)) {

		amdgpu_virt_init_setting(adev);

		xgpu_nv_mailbox_set_irq_funcs(adev);