Commit 089d1c31 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull kvm fixes from Paolo Bonzini:
"ARM:

   - Fix the pKVM stage-1 walker erronously using the stage-2 accessor

   - Correctly convert vcpu->kvm to a hyp pointer when generating an
     exception in a nVHE+MTE configuration

   - Check that KVM_CAP_DIRTY_LOG_* are valid before enabling them

   - Fix SMPRI_EL1/TPIDR2_EL0 trapping on VHE

   - Document the boot requirements for FGT when entering the kernel at
     EL1

  x86:

   - Use SRCU to protect zap in __kvm_set_or_clear_apicv_inhibit()

   - Make argument order consistent for kvcalloc()

   - Userspace API fixes for DEBUGCTL and LBRs"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: x86: Fix a typo about the usage of kvcalloc()
  KVM: x86: Use SRCU to protect zap in __kvm_set_or_clear_apicv_inhibit()
  KVM: VMX: Ignore guest CPUID for host userspace writes to DEBUGCTL
  KVM: VMX: Fold vmx_supported_debugctl() into vcpu_supported_debugctl()
  KVM: VMX: Advertise PMU LBRs if and only if perf supports LBRs
  arm64: booting: Document our requirements for fine grained traps with SME
  KVM: arm64: Fix SMPRI_EL1/TPIDR2_EL0 trapping on VHE
  KVM: Check KVM_CAP_DIRTY_LOG_{RING, RING_ACQ_REL} prior to enabling them
  KVM: arm64: Fix bad dereference on MTE-enabled systems
  KVM: arm64: Use correct accessor to parse stage-1 PTEs
parents 6e8c78d3 f4298cac

Documentation/arm64/booting.rst

+8 −0
Original line number Diff line number Diff line
@@ -340,6 +340,14 @@ Before jumping into the kernel, the following conditions must be met: 
    - SMCR_EL2.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



    - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.



    - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.



    - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.



    - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.



  For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64)



  - If EL3 is present:

arch/arm64/kvm/hyp/exception.c

+2 −1
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <hyp/adjust_pc.h>

#include <linux/kvm_host.h>

#include <asm/kvm_emulate.h>

#include <asm/kvm_mmu.h>



#if !defined (__KVM_NVHE_HYPERVISOR__) && !defined (__KVM_VHE_HYPERVISOR__)

#error Hypervisor code only!
@@ -115,7 +116,7 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode, 
	new |= (old & PSR_C_BIT);

	new |= (old & PSR_V_BIT);



	if (kvm_has_mte(vcpu->kvm))

	if (kvm_has_mte(kern_hyp_va(vcpu->kvm)))

		new |= PSR_TCO_BIT;



	new |= (old & PSR_DIT_BIT);

arch/arm64/kvm/hyp/include/hyp/switch.h

+20 −0
Original line number Diff line number Diff line
@@ -87,6 +87,17 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) 


	vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2);

	write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);



	if (cpus_have_final_cap(ARM64_SME)) {

		sysreg_clear_set_s(SYS_HFGRTR_EL2,

				   HFGxTR_EL2_nSMPRI_EL1_MASK |

				   HFGxTR_EL2_nTPIDR2_EL0_MASK,

				   0);

		sysreg_clear_set_s(SYS_HFGWTR_EL2,

				   HFGxTR_EL2_nSMPRI_EL1_MASK |

				   HFGxTR_EL2_nTPIDR2_EL0_MASK,

				   0);

	}

}



static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
@@ -96,6 +107,15 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) 
	write_sysreg(0, hstr_el2);

	if (kvm_arm_support_pmu_v3())

		write_sysreg(0, pmuserenr_el0);



	if (cpus_have_final_cap(ARM64_SME)) {

		sysreg_clear_set_s(SYS_HFGRTR_EL2, 0,

				   HFGxTR_EL2_nSMPRI_EL1_MASK |

				   HFGxTR_EL2_nTPIDR2_EL0_MASK);

		sysreg_clear_set_s(SYS_HFGWTR_EL2, 0,

				   HFGxTR_EL2_nSMPRI_EL1_MASK |

				   HFGxTR_EL2_nTPIDR2_EL0_MASK);

	}

}



static inline void ___activate_traps(struct kvm_vcpu *vcpu)

arch/arm64/kvm/hyp/nvhe/mem_protect.c

+1 −1
Original line number Diff line number Diff line
@@ -516,7 +516,7 @@ static enum pkvm_page_state hyp_get_page_state(kvm_pte_t pte) 
	if (!kvm_pte_valid(pte))

		return PKVM_NOPAGE;



	return pkvm_getstate(kvm_pgtable_stage2_pte_prot(pte));

	return pkvm_getstate(kvm_pgtable_hyp_pte_prot(pte));

}



static int __hyp_check_page_state_range(u64 addr, u64 size,

arch/arm64/kvm/hyp/nvhe/switch.c

+0 −26
Original line number Diff line number Diff line
@@ -55,18 +55,6 @@ static void __activate_traps(struct kvm_vcpu *vcpu) 
	write_sysreg(val, cptr_el2);

	write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2);



	if (cpus_have_final_cap(ARM64_SME)) {

		val = read_sysreg_s(SYS_HFGRTR_EL2);

		val &= ~(HFGxTR_EL2_nTPIDR2_EL0_MASK |

			 HFGxTR_EL2_nSMPRI_EL1_MASK);

		write_sysreg_s(val, SYS_HFGRTR_EL2);



		val = read_sysreg_s(SYS_HFGWTR_EL2);

		val &= ~(HFGxTR_EL2_nTPIDR2_EL0_MASK |

			 HFGxTR_EL2_nSMPRI_EL1_MASK);

		write_sysreg_s(val, SYS_HFGWTR_EL2);

	}



	if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {

		struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt;
@@ -110,20 +98,6 @@ static void __deactivate_traps(struct kvm_vcpu *vcpu) 


	write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2);



	if (cpus_have_final_cap(ARM64_SME)) {

		u64 val;



		val = read_sysreg_s(SYS_HFGRTR_EL2);

		val |= HFGxTR_EL2_nTPIDR2_EL0_MASK |

			HFGxTR_EL2_nSMPRI_EL1_MASK;

		write_sysreg_s(val, SYS_HFGRTR_EL2);



		val = read_sysreg_s(SYS_HFGWTR_EL2);

		val |= HFGxTR_EL2_nTPIDR2_EL0_MASK |

			HFGxTR_EL2_nSMPRI_EL1_MASK;

		write_sysreg_s(val, SYS_HFGWTR_EL2);

	}



	cptr = CPTR_EL2_DEFAULT;

	if (vcpu_has_sve(vcpu) && (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED))

		cptr |= CPTR_EL2_TZ;