Unverified Commit 088ec01f authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Palmer Dabbelt
Browse files

RISC-V: add rd reg parsing to insn.h header 



Add a macro to allow parsing of the rd register from an instruction.

Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Link: https://lore.kernel.org/r/20221223221332.4127602-11-heiko@sntech.de


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 8963d622

arch/riscv/include/asm/insn.h

+5 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
#define RVG_RS1_OPOFF		15

#define RVG_RS2_OPOFF		20

#define RVG_RD_OPOFF		7

#define RVG_RD_MASK		GENMASK(4, 0)



/* The bit field of immediate value in RVC J instruction */

#define RVC_J_IMM_SIGN_OPOFF	12
@@ -244,6 +245,10 @@ static __always_inline bool riscv_insn_is_branch(u32 code) 
#define RV_X(X, s, mask)  (((X) >> (s)) & (mask))

#define RVC_X(X, s, mask) RV_X(X, s, mask)



#define RV_EXTRACT_RD_REG(x) \

	({typeof(x) x_ = (x); \

	(RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })



#define RV_EXTRACT_UTYPE_IMM(x) \

	({typeof(x) x_ = (x); \

	(RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })