Commit 0874cf86 authored by Rajeev Nandan's avatar Rajeev Nandan Committed by Dmitry Baryshkov
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drm/msm/dsi: Add dsi phy tuning configuration support 



Add support for MSM DSI PHY tuning configuration. Current design is
to support drive strength and drive level/amplitude tuning for
10nm PHY version, but this can be extended to other PHY versions.

Signed-off-by: default avatarRajeev Nandan <quic_rajeevny@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1643573719-32095-3-git-send-email-quic_rajeevny@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 3bcf3d83

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+6 −0
Original line number Diff line number Diff line
@@ -741,6 +741,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) 
		}

	}



	if (phy->cfg->ops.parse_dt_properties) {

		ret = phy->cfg->ops.parse_dt_properties(phy);

		if (ret)

			goto fail;

	}



	ret = dsi_phy_regulator_init(phy);

	if (ret)

		goto fail;

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+4 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ struct msm_dsi_phy_ops { 
	void (*save_pll_state)(struct msm_dsi_phy *phy);

	int (*restore_pll_state)(struct msm_dsi_phy *phy);

	bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);

	int (*parse_dt_properties)(struct msm_dsi_phy *phy);

};



struct msm_dsi_phy_cfg {
@@ -82,6 +83,8 @@ struct msm_dsi_dphy_timing { 
#define DSI_PIXEL_PLL_CLK		1

#define NUM_PROVIDED_CLKS		2



#define DSI_LANE_MAX			5



struct msm_dsi_phy {

	struct platform_device *pdev;

	void __iomem *base;
@@ -99,6 +102,7 @@ struct msm_dsi_phy { 


	struct msm_dsi_dphy_timing timing;

	const struct msm_dsi_phy_cfg *cfg;

	void *tuning_cfg;



	enum msm_dsi_phy_usecase usecase;

	bool regulator_ldo_mode;