Commit 086ab943 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/cadence' 

- Fix bitmap size when searching for free outbound region (Dan Carpenter)

- Do device-specific setup to allow PTM Responder to be enabled (Christian
  Gmeiner)

- Don't advertise FLR in Device Capabilities register because the
  controller incorrectly resets Margining Lane Status and Margining Lane
  Control on FLR (Parshuram Thombare)

* remotes/lorenzo/pci/cadence:
  PCI: cadence: Clear FLR in device capabilities register
  PCI: cadence: Allow PTM Responder to be enabled
  PCI: cadence: Fix find_first_zero_bit() limit
parents 8d8b2669 95b00f68

drivers/pci/controller/cadence/pci-j721e.c

+3 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ struct j721e_pcie_data { 
	enum j721e_pcie_mode	mode;

	unsigned int		quirk_retrain_flag:1;

	unsigned int		quirk_detect_quiet_flag:1;

	unsigned int		quirk_disable_flr:1;

	u32			linkdown_irq_regfield;

	unsigned int		byte_access_allowed:1;

};
@@ -307,6 +308,7 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = { 
static const struct j721e_pcie_data j7200_pcie_ep_data = {

	.mode = PCI_MODE_EP,

	.quirk_detect_quiet_flag = true,

	.quirk_disable_flr = true,

};



static const struct j721e_pcie_data am64_pcie_rc_data = {
@@ -405,6 +407,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) 
			return -ENOMEM;



		ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;

		ep->quirk_disable_flr = data->quirk_disable_flr;



		cdns_pcie = &ep->pcie;

		cdns_pcie->dev = dev;

drivers/pci/controller/cadence/pcie-cadence-ep.c

+18 −3
Original line number Diff line number Diff line
@@ -187,8 +187,7 @@ static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, 
	struct cdns_pcie *pcie = &ep->pcie;

	u32 r;



	r = find_first_zero_bit(&ep->ob_region_map,

				sizeof(ep->ob_region_map) * BITS_PER_LONG);

	r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG);

	if (r >= ep->max_regions - 1) {

		dev_err(&epc->dev, "no free outbound region\n");

		return -EINVAL;
@@ -565,7 +564,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) 
	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);

	struct cdns_pcie *pcie = &ep->pcie;

	struct device *dev = pcie->dev;

	int ret;

	int max_epfs = sizeof(epc->function_num_map) * 8;

	int ret, value, epf;



	/*

	 * BIT(0) is hardwired to 1, hence function 0 is always enabled
@@ -573,6 +573,21 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) 
	 */

	cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map);



	if (ep->quirk_disable_flr) {

		for (epf = 0; epf < max_epfs; epf++) {

			if (!(epc->function_num_map & BIT(epf)))

				continue;



			value = cdns_pcie_ep_fn_readl(pcie, epf,

					CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +

					PCI_EXP_DEVCAP);

			value &= ~PCI_EXP_DEVCAP_FLR;

			cdns_pcie_ep_fn_writel(pcie, epf,

					CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +

					PCI_EXP_DEVCAP, value);

		}

	}



	ret = cdns_pcie_start_link(pcie);

	if (ret) {

		dev_err(dev, "Failed to start link\n");

drivers/pci/controller/cadence/pcie-cadence-host.c

+10 −0
Original line number Diff line number Diff line
@@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie) 
	return ret;

}



static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)

{

	u32 val;



	val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);

	cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);

}



static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)

{

	struct cdns_pcie *pcie = &rc->pcie;
@@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) 
	if (rc->quirk_detect_quiet_flag)

		cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);



	cdns_pcie_host_enable_ptm_response(pcie);



	ret = cdns_pcie_start_link(pcie);

	if (ret) {

		dev_err(dev, "Failed to start link\n");

drivers/pci/controller/cadence/pcie-cadence.h

+7 −0
Original line number Diff line number Diff line
@@ -116,6 +116,10 @@ 
#define LM_RC_BAR_CFG_APERTURE(bar, aperture)		\

					(((aperture) - 2) << ((bar) * 8))



/* PTM Control Register */

#define CDNS_PCIE_LM_PTM_CTRL 	(CDNS_PCIE_LM_BASE + 0x0da8)

#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN 	BIT(17)



/*

 * Endpoint Function Registers (PCI configuration space for endpoint functions)

 */
@@ -123,6 +127,7 @@ 


#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET	0x90

#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET	0xb0

#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET	0xc0

#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET	0x200



/*
@@ -357,6 +362,7 @@ struct cdns_pcie_epf { 
 *        minimize time between read and write

 * @epf: Structure to hold info about endpoint function

 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk

 * @quirk_disable_flr: Disable FLR (Function Level Reset) quirk flag

 */

struct cdns_pcie_ep {

	struct cdns_pcie	pcie;
@@ -372,6 +378,7 @@ struct cdns_pcie_ep { 
	spinlock_t		lock;

	struct cdns_pcie_epf	*epf;

	unsigned int		quirk_detect_quiet_flag:1;

	unsigned int		quirk_disable_flr:1;

};