Unverified Commit 08381767 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!4542 Support feature TLBI DVMBM

Merge Pull Request from: @ci-robot 
 
PR sync from: lishusen <lishusen2@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/HO5FDTP2Z527R4VERAOSHXMXHS7ODKZN/ 
Replace cpumask_t* by cpumask_var_t and rename related variables

Yanan Wang (1):
  KVM: arm64: Only probe Hisi ncsnp feature on Hisi CPUs

Zenghui Yu (2):
  KVM: arm64: Probe Hisi CPU TYPE from ACPI/DTB
  KVM: arm64: Add support for probing Hisi ncsnp capability

lishusen (5):
  KVM: arm64: Support a new HiSi CPU type
  KVM: arm64: Probe and configure DVMBM capability on HiSi CPUs
  KVM: arm64: Add kvm_vcpu_arch::sched_cpus and pre_sched_cpus
  KVM: arm64: Add kvm_arch::sched_cpus and sched_lock
  KVM: arm64: Implement the capability of DVMBM


-- 
2.33.0
 
https://gitee.com/openeuler/kernel/issues/I8TN8N 
 
Link:https://gitee.com/openeuler/kernel/pulls/4542

 

Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Reviewed-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Reviewed-by: default avatarLiu Chao <liuchao173@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 9a4fe2af d47f8143
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+4 −0
Original line number Diff line number Diff line
@@ -2654,6 +2654,10 @@
			[KVM,ARM] Allow use of GICv4 for direct injection of
			LPIs.

	kvm-arm.dvmbm_enabled=
			[KVM,ARM] Allow use of HiSilicon DVMBM capability.
			Default: 0

	kvm_cma_resv_ratio=n [PPC]
			Reserves given percentage from system memory area for
			contiguous memory allocation for KVM hash pagetable
+1 −0
Original line number Diff line number Diff line
@@ -732,6 +732,7 @@ CONFIG_KVM_VFIO=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
CONFIG_KVM_HISI_VIRT=y
CONFIG_KVM_XFER_TO_GUEST_WORK=y
CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
CONFIG_VIRTUALIZATION=y
+16 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@
#define KVM_REQ_RELOAD_PMU	KVM_ARCH_REQ(5)
#define KVM_REQ_SUSPEND		KVM_ARCH_REQ(6)
#define KVM_REQ_RESYNC_PMU_EL0	KVM_ARCH_REQ(7)
#define KVM_REQ_RELOAD_TLBI_DVMBM	KVM_ARCH_REQ(8)

#define KVM_DIRTY_LOG_MANUAL_CAPS   (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
				     KVM_DIRTY_LOG_INITIALLY_SET)
@@ -279,6 +280,12 @@ struct kvm_arch {
	 * the associated pKVM instance in the hypervisor.
	 */
	struct kvm_protected_vm pkvm;

#ifdef CONFIG_KVM_HISI_VIRT
	spinlock_t sched_lock;
	cpumask_var_t sched_cpus;	/* Union of all vcpu's cpus_ptr */
	u64 tlbi_dvmbm;
#endif
};

struct kvm_vcpu_fault_info {
@@ -591,6 +598,12 @@ struct kvm_vcpu_arch {

	/* Per-vcpu CCSIDR override or NULL */
	u32 *ccsidr;

#ifdef CONFIG_KVM_HISI_VIRT
	/* pCPUs this vCPU can be scheduled on. Pure copy of current->cpus_ptr */
	cpumask_var_t sched_cpus;
	cpumask_var_t pre_sched_cpus;
#endif
};

/*
@@ -1159,4 +1172,7 @@ extern unsigned int twedel;
void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);

extern bool kvm_ncsnp_support;
extern bool kvm_dvmbm_support;

#endif /* __ARM64_KVM_HOST_H__ */
+1 −1
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ static inline void __clean_dcache_guest_page(void *va, size_t size)
	 * faulting in pages. Furthermore, FWB implies IDC, so cleaning to
	 * PoU is not required either in this case.
	 */
	if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
	if (kvm_ncsnp_support || cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
		return;

	kvm_flush_dcache_to_poc(va, size);
+5 −0
Original line number Diff line number Diff line
@@ -111,6 +111,11 @@ KVM_NVHE_ALIAS(__hyp_rodata_end);
/* pKVM static key */
KVM_NVHE_ALIAS(kvm_protected_mode_initialized);

#ifdef CONFIG_KVM_HISI_VIRT
/* Capability of non-cacheable snooping */
KVM_NVHE_ALIAS(kvm_ncsnp_support);
#endif

#endif /* CONFIG_KVM */

#ifdef CONFIG_EFI_ZBOOT
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