Commit 07ff1d6f authored by Satya Priya Kakitapalli's avatar Satya Priya Kakitapalli Committed by Wen Zhiwei
Browse files

clk: qcom: gcc-sc8180x: Add GPLL9 support 

stable inclusion
from stable-v6.6.55
commit 712d30f9a505d4e797b2c1bba8314100a52d6939
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IB0MX4

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=712d30f9a505d4e797b2c1bba8314100a52d6939



--------------------------------

[ Upstream commit 818a2f8d5e4ad2c1e39a4290158fe8e39a744c70 ]

Add the missing GPLL9 pll and fix the gcc_parents_7 data to use
the correct pll hw.

Fixes: 4433594b ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarSatya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-3-8b3eaa5fb856@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarWen Zhiwei <wenzhiwei@kylinos.cn>
parent c2a84d2a

drivers/clk/qcom/gcc-sc8180x.c

+19 −1
Original line number Diff line number Diff line
@@ -142,6 +142,23 @@ static struct clk_alpha_pll gpll7 = { 
	},

};



static struct clk_alpha_pll gpll9 = {

	.offset = 0x1c000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],

	.clkr = {

		.enable_reg = 0x52000,

		.enable_mask = BIT(9),

		.hw.init = &(const struct clk_init_data) {

			.name = "gpll9",

			.parent_data = &(const struct clk_parent_data) {

				.fw_name = "bi_tcxo",

			},

			.num_parents = 1,

			.ops = &clk_alpha_pll_fixed_trion_ops,

		},

	},

};



static const struct parent_map gcc_parent_map_0[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },
@@ -241,7 +258,7 @@ static const struct parent_map gcc_parent_map_7[] = { 
static const struct clk_parent_data gcc_parents_7[] = {

	{ .fw_name = "bi_tcxo", },

	{ .hw = &gpll0.clkr.hw },

	{ .name = "gppl9" },

	{ .hw = &gpll9.clkr.hw },

	{ .hw = &gpll4.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

};
@@ -4419,6 +4436,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { 
	[GPLL1] = &gpll1.clkr,

	[GPLL4] = &gpll4.clkr,

	[GPLL7] = &gpll7.clkr,

	[GPLL9] = &gpll9.clkr,

};



static const struct qcom_reset_map gcc_sc8180x_resets[] = {