media: platform: Add Renesas RZ/G2L CRU driver

	  To compile this driver as a module, choose M here: the

	  module will be called rzg2l-csi2.

config VIDEO_RZG2L_CRU

	tristate "RZ/G2L Camera Receiving Unit (CRU) Driver"

	depends on ARCH_RENESAS || COMPILE_TEST

	depends on V4L_PLATFORM_DRIVERS

	depends on VIDEO_DEV && OF

	select MEDIA_CONTROLLER

	select V4L2_FWNODE

	select VIDEOBUF2_DMA_CONTIG

	select VIDEO_V4L2_SUBDEV_API

	help

	  Support for Renesas RZ/G2L (and alike SoC's) Camera Receiving

	  Unit (CRU) driver.

	  To compile this driver as a module, choose M here: the

	  module will be called rzg2l-cru.

# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_VIDEO_RZG2L_CSI2) += rzg2l-csi2.o

rzg2l-cru-objs = rzg2l-core.o rzg2l-ip.o rzg2l-video.o

obj-$(CONFIG_VIDEO_RZG2L_CRU) += rzg2l-cru.o

// SPDX-License-Identifier: GPL-2.0+

/*

 * Driver for Renesas RZ/G2L CRU

 *

 * Copyright (C) 2022 Renesas Electronics Corp.

 *

 * Based on Renesas R-Car VIN

 * Copyright (C) 2011-2013 Renesas Solutions Corp.

 * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com>

 * Copyright (C) 2008 Magnus Damm

 */

#include <linux/clk.h>

#include <linux/module.h>

#include <linux/mod_devicetable.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_graph.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>

#include <media/v4l2-fwnode.h>

#include <media/v4l2-mc.h>

#include "rzg2l-cru.h"

static inline struct rzg2l_cru_dev *notifier_to_cru(struct v4l2_async_notifier *n)

{

	return container_of(n, struct rzg2l_cru_dev, notifier);

}

static const struct media_device_ops rzg2l_cru_media_ops = {

	.link_notify = v4l2_pipeline_link_notify,

};

/* -----------------------------------------------------------------------------

 * Group async notifier

 */

static int rzg2l_cru_group_notify_complete(struct v4l2_async_notifier *notifier)

{

	struct rzg2l_cru_dev *cru = notifier_to_cru(notifier);

	struct media_entity *source, *sink;

	int ret;

	ret = rzg2l_cru_ip_subdev_register(cru);

	if (ret)

		return ret;

	ret = v4l2_device_register_subdev_nodes(&cru->v4l2_dev);

	if (ret) {

		dev_err(cru->dev, "Failed to register subdev nodes\n");

		return ret;

	}

	ret = rzg2l_cru_video_register(cru);

	if (ret)

		return ret;

	/*

	 * CRU can be connected either to CSI2 or PARALLEL device

	 * For now we are only supporting CSI2

	 *

	 * Create media device link between CSI-2 <-> CRU IP

	 */

	source = &cru->csi.subdev->entity;

	sink = &cru->ip.subdev.entity;

	ret = media_create_pad_link(source, 1, sink, 0,

				    MEDIA_LNK_FL_ENABLED |

				    MEDIA_LNK_FL_IMMUTABLE);

	if (ret) {

		dev_err(cru->dev, "Error creating link from %s to %s\n",

			source->name, sink->name);

		return ret;

	}

	cru->csi.channel = 0;

	cru->ip.remote = cru->csi.subdev;

	/* Create media device link between CRU IP <-> CRU OUTPUT */

	source = &cru->ip.subdev.entity;

	sink = &cru->vdev.entity;

	ret = media_create_pad_link(source, 1, sink, 0,

				    MEDIA_LNK_FL_ENABLED |

				    MEDIA_LNK_FL_IMMUTABLE);

	if (ret) {

		dev_err(cru->dev, "Error creating link from %s to %s\n",

			source->name, sink->name);

		return ret;

	}

	return 0;

}

static void rzg2l_cru_group_notify_unbind(struct v4l2_async_notifier *notifier,

					  struct v4l2_subdev *subdev,

					  struct v4l2_async_subdev *asd)

{

	struct rzg2l_cru_dev *cru = notifier_to_cru(notifier);

	rzg2l_cru_ip_subdev_unregister(cru);

	mutex_lock(&cru->mdev_lock);

	if (cru->csi.asd == asd) {

		cru->csi.subdev = NULL;

		dev_dbg(cru->dev, "Unbind CSI-2 %s\n", subdev->name);

	}

	mutex_unlock(&cru->mdev_lock);

}

static int rzg2l_cru_group_notify_bound(struct v4l2_async_notifier *notifier,

					struct v4l2_subdev *subdev,

					struct v4l2_async_subdev *asd)

{

	struct rzg2l_cru_dev *cru = notifier_to_cru(notifier);

	mutex_lock(&cru->mdev_lock);

	if (cru->csi.asd == asd) {

		cru->csi.subdev = subdev;

		dev_dbg(cru->dev, "Bound CSI-2 %s\n", subdev->name);

	}

	mutex_unlock(&cru->mdev_lock);

	return 0;

}

static const struct v4l2_async_notifier_operations rzg2l_cru_async_ops = {

	.bound = rzg2l_cru_group_notify_bound,

	.unbind = rzg2l_cru_group_notify_unbind,

	.complete = rzg2l_cru_group_notify_complete,

};

static int rzg2l_cru_mc_parse_of(struct rzg2l_cru_dev *cru)

{

	struct v4l2_fwnode_endpoint vep = {

		.bus_type = V4L2_MBUS_CSI2_DPHY,

	};

	struct fwnode_handle *ep, *fwnode;

	struct v4l2_async_subdev *asd;

	int ret;

	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(cru->dev), 1, 0, 0);

	if (!ep)

		return 0;

	fwnode = fwnode_graph_get_remote_endpoint(ep);

	ret = v4l2_fwnode_endpoint_parse(ep, &vep);

	fwnode_handle_put(ep);

	if (ret) {

		dev_err(cru->dev, "Failed to parse %pOF\n", to_of_node(fwnode));

		ret = -EINVAL;

		goto out;

	}

	if (!of_device_is_available(to_of_node(fwnode))) {

		dev_dbg(cru->dev, "OF device %pOF disabled, ignoring\n",

			to_of_node(fwnode));

		ret = -ENOTCONN;

		goto out;

	}

	asd = v4l2_async_nf_add_fwnode(&cru->notifier, fwnode,

				       struct v4l2_async_subdev);

	if (IS_ERR(asd)) {

		ret = PTR_ERR(asd);

		goto out;

	}

	cru->csi.asd = asd;

	dev_dbg(cru->dev, "Added OF device %pOF to slot %u\n",

		to_of_node(fwnode), vep.base.id);

out:

	fwnode_handle_put(fwnode);

	return ret;

}

static int rzg2l_cru_mc_parse_of_graph(struct rzg2l_cru_dev *cru)

{

	int ret;

	v4l2_async_nf_init(&cru->notifier);

	ret = rzg2l_cru_mc_parse_of(cru);

	if (ret)

		return ret;

	cru->notifier.ops = &rzg2l_cru_async_ops;

	if (list_empty(&cru->notifier.asd_list))

		return 0;

	ret = v4l2_async_nf_register(&cru->v4l2_dev, &cru->notifier);

	if (ret < 0) {

		dev_err(cru->dev, "Notifier registration failed\n");

		v4l2_async_nf_cleanup(&cru->notifier);

		return ret;

	}

	return 0;

}

static int rzg2l_cru_media_init(struct rzg2l_cru_dev *cru)

{

	struct media_device *mdev = NULL;

	const struct of_device_id *match;

	int ret;

	cru->pad.flags = MEDIA_PAD_FL_SINK;

	ret = media_entity_pads_init(&cru->vdev.entity, 1, &cru->pad);

	if (ret)

		return ret;

	mutex_init(&cru->mdev_lock);

	mdev = &cru->mdev;

	mdev->dev = cru->dev;

	mdev->ops = &rzg2l_cru_media_ops;

	match = of_match_node(cru->dev->driver->of_match_table,

			      cru->dev->of_node);

	strscpy(mdev->driver_name, KBUILD_MODNAME, sizeof(mdev->driver_name));

	strscpy(mdev->model, match->compatible, sizeof(mdev->model));

	cru->v4l2_dev.mdev = &cru->mdev;

	media_device_init(mdev);

	ret = rzg2l_cru_mc_parse_of_graph(cru);

	if (ret) {

		mutex_lock(&cru->mdev_lock);

		cru->v4l2_dev.mdev = NULL;

		mutex_unlock(&cru->mdev_lock);

	}

	return 0;

}

static int rzg2l_cru_probe(struct platform_device *pdev)

{

	struct rzg2l_cru_dev *cru;

	int ret;

	cru = devm_kzalloc(&pdev->dev, sizeof(*cru), GFP_KERNEL);

	if (!cru)

		return -ENOMEM;

	cru->base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(cru->base))

		return PTR_ERR(cru->base);

	cru->presetn = devm_reset_control_get_shared(&pdev->dev, "presetn");

	if (IS_ERR(cru->presetn))

		return dev_err_probe(&pdev->dev, PTR_ERR(cru->presetn),

				     "Failed to get cpg presetn\n");

	cru->aresetn = devm_reset_control_get_exclusive(&pdev->dev, "aresetn");

	if (IS_ERR(cru->aresetn))

		return dev_err_probe(&pdev->dev, PTR_ERR(cru->aresetn),

				     "Failed to get cpg aresetn\n");

	cru->vclk = devm_clk_get(&pdev->dev, "video");

	if (IS_ERR(cru->vclk))

		return dev_err_probe(&pdev->dev, PTR_ERR(cru->vclk),

				     "Failed to get video clock\n");

	cru->dev = &pdev->dev;

	cru->info = of_device_get_match_data(&pdev->dev);

	cru->image_conv_irq = platform_get_irq(pdev, 0);

	if (cru->image_conv_irq < 0)

		return cru->image_conv_irq;

	platform_set_drvdata(pdev, cru);

	ret = rzg2l_cru_dma_register(cru);

	if (ret)

		return ret;

	cru->num_buf = RZG2L_CRU_HW_BUFFER_DEFAULT;

	pm_suspend_ignore_children(&pdev->dev, true);

	pm_runtime_enable(&pdev->dev);

	ret = rzg2l_cru_media_init(cru);

	if (ret)

		goto error_dma_unregister;

	return 0;

error_dma_unregister:

	rzg2l_cru_dma_unregister(cru);

	pm_runtime_disable(&pdev->dev);

	return ret;

}

static int rzg2l_cru_remove(struct platform_device *pdev)

{

	struct rzg2l_cru_dev *cru = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);

	v4l2_async_nf_unregister(&cru->notifier);

	v4l2_async_nf_cleanup(&cru->notifier);

	rzg2l_cru_video_unregister(cru);

	media_device_cleanup(&cru->mdev);

	mutex_destroy(&cru->mdev_lock);

	rzg2l_cru_dma_unregister(cru);

	return 0;

}

static const struct of_device_id rzg2l_cru_of_id_table[] = {

	{ .compatible = "renesas,rzg2l-cru", },

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(of, rzg2l_cru_of_id_table);

static struct platform_driver rzg2l_cru_driver = {

	.driver = {

		.name = "rzg2l-cru",

		.of_match_table = rzg2l_cru_of_id_table,

	},

	.probe = rzg2l_cru_probe,

	.remove = rzg2l_cru_remove,

};

module_platform_driver(rzg2l_cru_driver);

MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");

MODULE_DESCRIPTION("Renesas RZ/G2L CRU driver");

MODULE_LICENSE("GPL");

/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Driver for Renesas RZ/G2L CRU

 *

 * Copyright (C) 2022 Renesas Electronics Corp.

 */

#ifndef __RZG2L_CRU__

#define __RZG2L_CRU__

#include <linux/reset.h>

#include <media/v4l2-async.h>

#include <media/v4l2-dev.h>

#include <media/v4l2-device.h>

#include <media/videobuf2-v4l2.h>

/* Number of HW buffers */

#define RZG2L_CRU_HW_BUFFER_MAX		8

#define RZG2L_CRU_HW_BUFFER_DEFAULT	3

/* Address alignment mask for HW buffers */

#define RZG2L_CRU_HW_BUFFER_MASK	0x1ff

/* Maximum number of CSI2 virtual channels */

#define RZG2L_CRU_CSI2_VCHANNEL		4

#define RZG2L_CRU_MIN_INPUT_WIDTH	320

#define RZG2L_CRU_MAX_INPUT_WIDTH	2800

#define RZG2L_CRU_MIN_INPUT_HEIGHT	240

#define RZG2L_CRU_MAX_INPUT_HEIGHT	4095

/**

 * enum rzg2l_cru_dma_state - DMA states

 * @RZG2L_CRU_DMA_STOPPED:   No operation in progress

 * @RZG2L_CRU_DMA_STARTING:  Capture starting up

 * @RZG2L_CRU_DMA_RUNNING:   Operation in progress have buffers

 * @RZG2L_CRU_DMA_STOPPING:  Stopping operation

 */

enum rzg2l_cru_dma_state {

	RZG2L_CRU_DMA_STOPPED = 0,

	RZG2L_CRU_DMA_STARTING,

	RZG2L_CRU_DMA_RUNNING,

	RZG2L_CRU_DMA_STOPPING,

};

struct rzg2l_cru_csi {

	struct v4l2_async_subdev *asd;

	struct v4l2_subdev *subdev;

	u32 channel;

};

struct rzg2l_cru_ip {

	struct v4l2_subdev subdev;

	struct media_pad pads[2];

	struct v4l2_async_notifier notifier;

	struct v4l2_subdev *remote;

};

/**

 * struct rzg2l_cru_dev - Renesas CRU device structure

 * @dev:		(OF) device

 * @base:		device I/O register space remapped to virtual memory

 * @info:		info about CRU instance

 *

 * @presetn:		CRU_PRESETN reset line

 * @aresetn:		CRU_ARESETN reset line

 *

 * @vclk:		CRU Main clock

 *

 * @vdev:		V4L2 video device associated with CRU

 * @v4l2_dev:		V4L2 device

 * @num_buf:		Holds the current number of buffers enabled

 * @notifier:		V4L2 asynchronous subdevs notifier

 *

 * @ip:			Image processing subdev info

 * @csi:		CSI info

 * @mdev:		media device

 * @mdev_lock:		protects the count, notifier and csi members

 * @pad:		media pad for the video device entity

 *

 * @lock:		protects @queue

 * @queue:		vb2 buffers queue

 * @scratch:		cpu address for scratch buffer

 * @scratch_phys:	physical address of the scratch buffer

 *

 * @qlock:		protects @queue_buf, @buf_list, @sequence

 *			@state

 * @queue_buf:		Keeps track of buffers given to HW slot

 * @buf_list:		list of queued buffers

 * @sequence:		V4L2 buffers sequence number

 * @state:		keeps track of operation state

 *

 * @format:		active V4L2 pixel format

 */

struct rzg2l_cru_dev {

	struct device *dev;

	void __iomem *base;

	const struct rzg2l_cru_info *info;

	struct reset_control *presetn;

	struct reset_control *aresetn;

	struct clk *vclk;

	int image_conv_irq;

	struct video_device vdev;

	struct v4l2_device v4l2_dev;

	u8 num_buf;

	struct v4l2_async_notifier notifier;

	struct rzg2l_cru_ip ip;

	struct rzg2l_cru_csi csi;

	struct media_device mdev;

	struct mutex mdev_lock;

	struct media_pad pad;

	struct mutex lock;

	struct vb2_queue queue;

	void *scratch;

	dma_addr_t scratch_phys;

	spinlock_t qlock;

	struct vb2_v4l2_buffer *queue_buf[RZG2L_CRU_HW_BUFFER_MAX];

	struct list_head buf_list;

	unsigned int sequence;

	enum rzg2l_cru_dma_state state;

	struct v4l2_pix_format format;

};

void rzg2l_cru_vclk_unprepare(struct rzg2l_cru_dev *cru);

int rzg2l_cru_vclk_prepare(struct rzg2l_cru_dev *cru);

int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru);

void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru);

int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru);

void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru);

int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru);

void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru);

const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format);

int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru);

void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru);

struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru);

#endif

// SPDX-License-Identifier: GPL-2.0

/*

 * Driver for Renesas RZ/G2L CRU

 *

 * Copyright (C) 2022 Renesas Electronics Corp.

 */

#include "rzg2l-cru.h"

struct rzg2l_cru_ip_format {

	u32 code;

	unsigned int datatype;

	unsigned int bpp;

};

static const struct rzg2l_cru_ip_format rzg2l_cru_ip_formats[] = {

	{ .code = MEDIA_BUS_FMT_UYVY8_1X16,	.datatype = 0x1e, .bpp = 16 },

};

enum rzg2l_csi2_pads {

	RZG2L_CRU_IP_SINK = 0,

	RZG2L_CRU_IP_SOURCE,

};

static const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int code)

{

	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(rzg2l_cru_ip_formats); i++)

		if (rzg2l_cru_ip_formats[i].code == code)

			return &rzg2l_cru_ip_formats[i];

	return NULL;

}

struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru)

{

	struct v4l2_subdev_state *state;

	struct v4l2_mbus_framefmt *fmt;

	state = v4l2_subdev_lock_and_get_active_state(&cru->ip.subdev);

	fmt = v4l2_subdev_get_pad_format(&cru->ip.subdev, state, 1);

	v4l2_subdev_unlock_state(state);

	return fmt;

}

static int rzg2l_cru_ip_s_stream(struct v4l2_subdev *sd, int enable)

{

	struct rzg2l_cru_dev *cru;

	int s_stream_ret = 0;

	int ret;

	cru = v4l2_get_subdevdata(sd);

	if (!enable) {

		ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable);

		if (ret)

			s_stream_ret = ret;

		ret = v4l2_subdev_call(cru->ip.remote, video, post_streamoff);

		if (ret == -ENOIOCTLCMD)

			ret = 0;

		if (ret && !s_stream_ret)

			s_stream_ret = ret;

		rzg2l_cru_stop_image_processing(cru);

	} else {

		ret = v4l2_subdev_call(cru->ip.remote, video, pre_streamon, 0);

		if (ret == -ENOIOCTLCMD)

			ret = 0;

		if (ret)

			return ret;

		ret = rzg2l_cru_start_image_processing(cru);

		if (ret) {

			v4l2_subdev_call(cru->ip.remote, video, post_streamoff);

			return ret;

		}

		rzg2l_cru_vclk_unprepare(cru);

		ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable);

		if (ret == -ENOIOCTLCMD)

			ret = 0;

		if (!ret) {

			ret = rzg2l_cru_vclk_prepare(cru);

			if (!ret)

				return 0;

		} else {

			/* enable back vclk so that s_stream in error path disables it */

			if (rzg2l_cru_vclk_prepare(cru))

				dev_err(cru->dev, "Failed to enable vclk\n");

		}

		s_stream_ret = ret;

		v4l2_subdev_call(cru->ip.remote, video, post_streamoff);

		rzg2l_cru_stop_image_processing(cru);

	}

	return s_stream_ret;

}

static int rzg2l_cru_ip_set_format(struct v4l2_subdev *sd,

				   struct v4l2_subdev_state *state,

				   struct v4l2_subdev_format *fmt)

{

	struct v4l2_mbus_framefmt *src_format;

	struct v4l2_mbus_framefmt *sink_format;

	src_format = v4l2_subdev_get_pad_format(sd, state, RZG2L_CRU_IP_SOURCE);

	if (fmt->pad == RZG2L_CRU_IP_SOURCE) {

		fmt->format = *src_format;

		return 0;

	}

	sink_format = v4l2_subdev_get_pad_format(sd, state, fmt->pad);

	if (!rzg2l_cru_ip_code_to_fmt(fmt->format.code))

		sink_format->code = rzg2l_cru_ip_formats[0].code;

	else

		sink_format->code = fmt->format.code;

	sink_format->field = V4L2_FIELD_NONE;

	sink_format->colorspace = fmt->format.colorspace;

	sink_format->xfer_func = fmt->format.xfer_func;

	sink_format->ycbcr_enc = fmt->format.ycbcr_enc;

	sink_format->quantization = fmt->format.quantization;

	sink_format->width = clamp_t(u32, fmt->format.width,

				     RZG2L_CRU_MIN_INPUT_WIDTH, RZG2L_CRU_MAX_INPUT_WIDTH);

	sink_format->height = clamp_t(u32, fmt->format.height,

				      RZG2L_CRU_MIN_INPUT_HEIGHT, RZG2L_CRU_MAX_INPUT_HEIGHT);

	fmt->format = *sink_format;

	/* propagate format to source pad */

	*src_format = *sink_format;

	return 0;

}

static int rzg2l_cru_ip_enum_mbus_code(struct v4l2_subdev *sd,

				       struct v4l2_subdev_state *state,

				       struct v4l2_subdev_mbus_code_enum *code)

{

	if (code->index >= ARRAY_SIZE(rzg2l_cru_ip_formats))

		return -EINVAL;

	code->code = rzg2l_cru_ip_formats[code->index].code;

	return 0;

}

static int rzg2l_cru_ip_enum_frame_size(struct v4l2_subdev *sd,

					struct v4l2_subdev_state *state,

					struct v4l2_subdev_frame_size_enum *fse)

{

	if (fse->index != 0)

		return -EINVAL;

	if (fse->code != MEDIA_BUS_FMT_UYVY8_1X16)

		return -EINVAL;

	fse->min_width = RZG2L_CRU_MIN_INPUT_WIDTH;

	fse->min_height = RZG2L_CRU_MIN_INPUT_HEIGHT;

	fse->max_width = RZG2L_CRU_MAX_INPUT_WIDTH;

	fse->max_height = RZG2L_CRU_MAX_INPUT_HEIGHT;

	return 0;

}

static int rzg2l_cru_ip_init_config(struct v4l2_subdev *sd,

				    struct v4l2_subdev_state *sd_state)

{

	struct v4l2_subdev_format fmt = { .pad = RZG2L_CRU_IP_SINK, };

	fmt.format.width = RZG2L_CRU_MIN_INPUT_WIDTH;

	fmt.format.height = RZG2L_CRU_MIN_INPUT_HEIGHT;

	fmt.format.field = V4L2_FIELD_NONE;

	fmt.format.code = MEDIA_BUS_FMT_UYVY8_1X16;

	fmt.format.colorspace = V4L2_COLORSPACE_SRGB;

	fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;

	fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT;

	fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT;

	return rzg2l_cru_ip_set_format(sd, sd_state, &fmt);

}

static const struct v4l2_subdev_video_ops rzg2l_cru_ip_video_ops = {

	.s_stream = rzg2l_cru_ip_s_stream,

};

static const struct v4l2_subdev_pad_ops rzg2l_cru_ip_pad_ops = {

	.enum_mbus_code = rzg2l_cru_ip_enum_mbus_code,

	.enum_frame_size = rzg2l_cru_ip_enum_frame_size,

	.init_cfg = rzg2l_cru_ip_init_config,

	.get_fmt = v4l2_subdev_get_fmt,

	.set_fmt = rzg2l_cru_ip_set_format,