Commit 07fa917a authored by Vinod Koul's avatar Vinod Koul Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8450: add ufs nodes 



Add the UFS and QMP PHY node for SM8450 SoC

Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215043440.605624-8-vkoul@kernel.org
parent 128914ad

arch/arm64/boot/dts/qcom/sm8450.dtsi

+72 −0
Original line number Diff line number Diff line
@@ -815,6 +815,78 @@ 
				clocks = <&xo_board>;

			};

		};



		ufs_mem_hc: ufshc@1d84000 {

			compatible = "qcom,sm8450-ufshc", "qcom,ufshc",

				     "jedec,ufs-2.0";

			reg = <0 0x01d84000 0 0x3000>;

			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

			phys = <&ufs_mem_phy_lanes>;

			phy-names = "ufsphy";

			lanes-per-direction = <2>;

			#reset-cells = <1>;

			resets = <&gcc GCC_UFS_PHY_BCR>;

			reset-names = "rst";



			power-domains = <&gcc UFS_PHY_GDSC>;



			iommus = <&apps_smmu 0xe0 0x0>;



			clock-names =

				"core_clk",

				"bus_aggr_clk",

				"iface_clk",

				"core_clk_unipro",

				"ref_clk",

				"tx_lane0_sync_clk",

				"rx_lane0_sync_clk",

				"rx_lane1_sync_clk";

			clocks =

				<&gcc GCC_UFS_PHY_AXI_CLK>,

				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

				<&gcc GCC_UFS_PHY_AHB_CLK>,

				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

				<&rpmhcc RPMH_CXO_CLK>,

				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

			freq-table-hz =

				<75000000 300000000>,

				<0 0>,

				<0 0>,

				<75000000 300000000>,

				<75000000 300000000>,

				<0 0>,

				<0 0>,

				<0 0>;

			status = "disabled";

		};



		ufs_mem_phy: phy@1d87000 {

			compatible = "qcom,sm8450-qmp-ufs-phy";

			reg = <0 0x01d87000 0 0xe10>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			clock-names = "ref", "ref_aux", "qref";

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,

				 <&gcc GCC_UFS_0_CLKREF_EN>;



			resets = <&ufs_mem_hc 0>;

			reset-names = "ufsphy";

			status = "disabled";



			ufs_mem_phy_lanes: lanes@1d87400 {

				reg = <0 0x01d87400 0 0x108>,

				      <0 0x01d87600 0 0x1e0>,

				      <0 0x01d87c00 0 0x1dc>,

				      <0 0x01d87800 0 0x108>,

				      <0 0x01d87a00 0 0x1e0>;

				#phy-cells = <0>;

				#clock-cells = <0>;

			};

		};

	};



	timer {