Commit 0785c8a6 authored Jul 31, 2024 by Yicong Yang Committed by zhangshuowen96 Oct 15, 2024

ACPI/IORT: Add PMCG platform information for HiSilicon HIP10/11

mainline inclusion
from mainline-v6.12-rc1
commit f3b78b470f28bb2a3a40e88bdf5c6de6a35a9b76
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IAWA07
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f3b78b470f28bb2a3a40e88bdf5c6de6a35a9b76



----------------------------------------------------------------------

HiSilicon HIP10/11 platforms using the same SMMU PMCG with HIP09
and thus suffers the same erratum. List them in the PMCG platform
information list without introducing a new SMMU PMCG Model.

Update the silicon-errata.rst as well.

Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Link: https://lore.kernel.org/r/20240731092658.11012-1-yangyicong@huawei.com


Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: zhangshuowen96 <zhangshuowen@hisilicon.com>

parent 0fac4b66

Documentation/arch/arm64/silicon-errata.rst

+2 −2

Original line number	Diff line number	Diff line
		@@ -202,8 +202,8 @@ stable kernels.
		+----------------+-----------------+-----------------+-----------------------------+
		\| Hisilicon \| Hip08 SMMU PMCG \| #162001800 \| N/A \|
		+----------------+-----------------+-----------------+-----------------------------+
		\| Hisilicon \| Hip08 SMMU PMCG \| #162001900 \| N/A \|
		\| \| Hip09 SMMU PMCG \| \| \|
		\| Hisilicon \| Hip{08,09,10,10C\| #162001900 \| N/A \|
		\| \| ,11} SMMU PMCG \| \| \|
		+----------------+-----------------+-----------------+-----------------------------+
		\| Hisilicon \| LINXICORE9100 \| #162100125 \| HISILICON_ERRATUM_162100125 \|
		+----------------+-----------------+-----------------+-----------------------------+

drivers/acpi/arm64/iort.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -1712,6 +1712,13 @@ static struct acpi_platform_list pmcg_plat_info[] __initdata = {
		/* HiSilicon Hip09 Platform */
		{"HISI ", "HIP09 ", 0, ACPI_SIG_IORT, greater_than_or_equal,
		"Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
		/* HiSilicon Hip10/11 Platform uses the same SMMU IP with Hip09 */
		{"HISI ", "HIP10 ", 0, ACPI_SIG_IORT, greater_than_or_equal,
		"Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
		{"HISI ", "HIP10C ", 0, ACPI_SIG_IORT, greater_than_or_equal,
		"Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
		{"HISI ", "HIP11 ", 0, ACPI_SIG_IORT, greater_than_or_equal,
		"Erratum #162001900", IORT_SMMU_V3_PMCG_HISI_HIP09},
		{ }
		};