Commit 078397bb authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates 



128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD
register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b
TPS2 for channel equalization.

v2: Use intel_dp_is_uhbr

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/723b29223dc570c8b63c3c6fe5fb772d9db06c0d.1631191763.git.jani.nikula@intel.com
parent 4e718a0e

drivers/gpu/drm/i915/display/intel_dp_link_training.c

+7 −3
Original line number Diff line number Diff line
@@ -602,9 +602,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 
}



/*

 * Pick training pattern for channel equalization. Training pattern 4 for HBR3

 * or for 1.4 devices that support it, training Pattern 3 for HBR2

 * or 1.2 devices that support it, Training Pattern 2 otherwise.

 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2

 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or

 * 1.2 devices that support it, TPS2 otherwise.

 */

static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,

				     const struct intel_crtc_state *crtc_state,
@@ -612,6 +612,10 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 
{

	bool source_tps3, sink_tps3, source_tps4, sink_tps4;



	/* UHBR+ use separate 128b/132b TPS2 */

	if (intel_dp_is_uhbr(crtc_state))

		return DP_TRAINING_PATTERN_2;



	/*

	 * Intel platforms that support HBR3 also support TPS4. It is mandatory

	 * for all downstream devices that support HBR3. There are no known eDP