Commit 077a4fa9 authored by Jim Quinlan's avatar Jim Quinlan Committed by Lorenzo Pieralisi
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PCI: brcmstb: Fix window register offset from 4 to 8 

The outbound memory window registers were being referenced
with an incorrect stride offset.  This probably wasn't noticed
previously as there was likely only one such window employed.


Link: https://lore.kernel.org/r/20200507201544.43432-3-james.quinlan@broadcom.com


Fixes: c0452137 ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
Signed-off-by: default avatarJim Quinlan <jquinlan@broadcom.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: default avatarNicolas Saenz Julienne <nsaenzjulienne@suse.de>
parent b382e4a0

drivers/pci/controller/pcie-brcmstb.c

+2 −2
Original line number Diff line number Diff line
@@ -54,11 +54,11 @@ 


#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c

#define PCIE_MEM_WIN0_LO(win)	\

		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)

		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)



#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010

#define PCIE_MEM_WIN0_HI(win)	\

		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)

		PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)



#define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c

#define  PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK		0x1f