Loading drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +3 −3 Original line number Diff line number Diff line Loading @@ -1516,11 +1516,11 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) } switch ((ctrl & 0x000f0000) >> 16) { case 6: datarate = pclk * 30 / 8; break; case 5: datarate = pclk * 24 / 8; break; case 6: datarate = pclk * 30; break; case 5: datarate = pclk * 24; break; case 2: default: datarate = pclk * 18 / 8; datarate = pclk * 18; break; } Loading drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c +3 −3 Original line number Diff line number Diff line Loading @@ -1159,11 +1159,11 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) if (outp->info.type == DCB_OUTPUT_DP) { u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300)); switch ((sync & 0x000003c0) >> 6) { case 6: pclk = pclk * 30 / 8; break; case 5: pclk = pclk * 24 / 8; break; case 6: pclk = pclk * 30; break; case 5: pclk = pclk * 24; break; case 2: default: pclk = pclk * 18 / 8; pclk = pclk * 18; break; } Loading drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c +5 −3 Original line number Diff line number Diff line Loading @@ -34,7 +34,7 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait) struct nvkm_output_dp *outp = (void *)base; bool retrain = true; u8 link[2], stat[3]; u32 rate; u32 linkrate; int ret, i; /* check that the link is trained at a high enough rate */ Loading @@ -44,8 +44,10 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait) goto done; } rate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET); if (rate < ((datarate / 8) * 10)) { linkrate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET); linkrate = (linkrate * 8) / 10; /* 8B/10B coding overhead */ datarate = (datarate + 9) / 10; /* -> decakilobits */ if (linkrate < datarate) { DBG("link not trained at sufficient rate\n"); goto done; } Loading Loading
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +3 −3 Original line number Diff line number Diff line Loading @@ -1516,11 +1516,11 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) } switch ((ctrl & 0x000f0000) >> 16) { case 6: datarate = pclk * 30 / 8; break; case 5: datarate = pclk * 24 / 8; break; case 6: datarate = pclk * 30; break; case 5: datarate = pclk * 24; break; case 2: default: datarate = pclk * 18 / 8; datarate = pclk * 18; break; } Loading
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c +3 −3 Original line number Diff line number Diff line Loading @@ -1159,11 +1159,11 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) if (outp->info.type == DCB_OUTPUT_DP) { u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300)); switch ((sync & 0x000003c0) >> 6) { case 6: pclk = pclk * 30 / 8; break; case 5: pclk = pclk * 24 / 8; break; case 6: pclk = pclk * 30; break; case 5: pclk = pclk * 24; break; case 2: default: pclk = pclk * 18 / 8; pclk = pclk * 18; break; } Loading
drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c +5 −3 Original line number Diff line number Diff line Loading @@ -34,7 +34,7 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait) struct nvkm_output_dp *outp = (void *)base; bool retrain = true; u8 link[2], stat[3]; u32 rate; u32 linkrate; int ret, i; /* check that the link is trained at a high enough rate */ Loading @@ -44,8 +44,10 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait) goto done; } rate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET); if (rate < ((datarate / 8) * 10)) { linkrate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET); linkrate = (linkrate * 8) / 10; /* 8B/10B coding overhead */ datarate = (datarate + 9) / 10; /* -> decakilobits */ if (linkrate < datarate) { DBG("link not trained at sufficient rate\n"); goto done; } Loading