Commit 0709e55e authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Florian Fainelli
Browse files

arm64: dts: broadcom: add missing cache properties 



As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  bcm94908.dtb: l2-cache0: 'cache-unified' is a required property

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarWilliam Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20230421223208.115555-1-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent ac9a7868

arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ 
		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};

arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
		L2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};