Unverified Commit 06f5a659 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!12314 [openEuler-24.03-LTS][linux-6.6.y sync] Backport 6.6.52-6.6.53 LTS Patches 

Merge Pull Request from: @wenzhiwei11 
 
git log --oneline v6.6.52..v6.6.53 | wc -l
54
50+4
Merged commits(4)

wifi: iwlwifi: mvm: don't wait for tx queues if firmware is dead
ocfs2: add bounds checking to ocfs2_xattr_find_entry()
ocfs2: strict bound check before memcmp in ocfs2_xattr_find_entry()
USB: usbtmc: prevent kernel-usb-infoleak 
 
Link:https://gitee.com/openeuler/kernel/pulls/12314

 

Reviewed-by: default avatarZhang Peng <zhangpeng362@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents b436b5d3 c9a7ad34

arch/loongarch/include/asm/hw_irq.h

+2 −0
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ 


extern atomic_t irq_err_count;



#define ARCH_IRQ_INIT_FLAGS	IRQ_NOPROBE



/*

 * interrupt-retrigger: NOP for now. This may not be appropriate for all

 * machines, we'll see ...

arch/loongarch/kernel/irq.c

+0 −3
Original line number Diff line number Diff line
@@ -150,9 +150,6 @@ void __init init_IRQ(void) 
	smp_ops.init_ipi();

#endif



	for (i = 0; i < NR_IRQS; i++)

		irq_set_noprobe(i);



	for_each_possible_cpu(i) {

		page = alloc_pages_node(cpu_to_node(i), GFP_KERNEL, order);

arch/microblaze/mm/init.c

+0 −5
Original line number Diff line number Diff line
@@ -193,11 +193,6 @@ asmlinkage void __init mmu_init(void) 
{

	unsigned int kstart, ksize;



	if (!memblock.reserved.cnt) {

		pr_emerg("Error memory count\n");

		machine_restart(NULL);

	}



	if ((u32) memblock.memory.regions[0].size < 0x400000) {

		pr_emerg("Memory must be greater than 4MB\n");

		machine_restart(NULL);

arch/x86/kernel/cpu/mshyperv.c

+1 −0
Original line number Diff line number Diff line
@@ -423,6 +423,7 @@ static void __init ms_hyperv_init_platform(void) 
	    ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {

		x86_platform.calibrate_tsc = hv_get_tsc_khz;

		x86_platform.calibrate_cpu = hv_get_tsc_khz;

		setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);

	}



	if (ms_hyperv.priv_high & HV_ISOLATION) {

arch/x86/mm/init.c

+6 −10
Original line number Diff line number Diff line
@@ -261,21 +261,17 @@ static void __init probe_page_size_mask(void) 
	}

}



#define INTEL_MATCH(_model) { .vendor  = X86_VENDOR_INTEL,	\

			      .family  = 6,			\

			      .model = _model,			\

			    }

/*

 * INVLPG may not properly flush Global entries

 * on these CPUs when PCIDs are enabled.

 */

static const struct x86_cpu_id invlpg_miss_ids[] = {

	INTEL_MATCH(INTEL_FAM6_ALDERLAKE   ),

	INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ),

	INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT ),

	INTEL_MATCH(INTEL_FAM6_RAPTORLAKE  ),

	INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P),

	INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,      0),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,    0),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, 0),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,     0),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,   0),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,   0),

	{}

};