Commit 06db7fde authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fifo: add new channel classes 



Exposes a bunch of the new features that became possible as a result
of the earlier commits.  DRM will build on this in the future to add
support for features such as SCG ("async compute") and multi-device
rendering, as part of the work necessary to be able to write a half-
decent vulkan driver - finally.

For the moment, this just crudely ports DRM to the API changes.

- channel class interfaces now the same for all HW classes
- channel group class exposed (SCG)
- channel runqueue selector exposed (SCG)
- channel sub-device id control exposed (multi-device rendering)
- channel names in logging will reflect creating process, not fd owner
- explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer
- drm is smarter about determining the appropriate channel class to use

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent 7ac29332

drivers/gpu/drm/nouveau/include/nvif/cl006b.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

#ifndef __NVIF_CL006B_H__

#define __NVIF_CL006B_H__



struct nv03_channel_dma_v0 {

	__u8  version;

	__u8  chid;

	__u8  pad02[2];

	__u32 offset;

	__u64 pushbuf;

};

#endif

drivers/gpu/drm/nouveau/include/nvif/cl506e.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

#ifndef __NVIF_CL506E_H__

#define __NVIF_CL506E_H__



struct nv50_channel_dma_v0 {

	__u8  version;

	__u8  chid;

	__u8  pad02[6];

	__u64 vmm;

	__u64 pushbuf;

	__u64 offset;

};

#endif

drivers/gpu/drm/nouveau/include/nvif/cl506f.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

#ifndef __NVIF_CL506F_H__

#define __NVIF_CL506F_H__



struct nv50_channel_gpfifo_v0 {

	__u8  version;

	__u8  chid;

	__u8  pad02[2];

	__u32 ilength;

	__u64 ioffset;

	__u64 pushbuf;

	__u64 vmm;

};

#endif

drivers/gpu/drm/nouveau/include/nvif/cl826e.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

#ifndef __NVIF_CL826E_H__

#define __NVIF_CL826E_H__



struct g82_channel_dma_v0 {

	__u8  version;

	__u8  chid;

	__u8  pad02[6];

	__u64 vmm;

	__u64 pushbuf;

	__u64 offset;

};

#endif

drivers/gpu/drm/nouveau/include/nvif/cl826f.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

#ifndef __NVIF_CL826F_H__

#define __NVIF_CL826F_H__



struct g82_channel_gpfifo_v0 {

	__u8  version;

	__u8  chid;

	__u8  pad02[2];

	__u32 ilength;

	__u64 ioffset;

	__u64 pushbuf;

	__u64 vmm;

};

#endif