Commit 06b224d5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.15-2021-09-01' of... 

Merge tag 'amd-drm-next-5.15-2021-09-01' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-5.15-2021-09-01:

amdgpu:
- Misc cleanups, typo fixes
- EEPROM fix
- Add some new PCI IDs
- Scatter/Gather display support for Yellow Carp
- PCIe DPM fix for RKL platforms
- RAS fix

amdkfd:
- SVM fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210901214015.4488-1-alexander.deucher@amd.com
parents 1645cca9 d6043581

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

+33 −17
Original line number Diff line number Diff line
@@ -468,14 +468,18 @@ bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *ade 
	return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;

}



/*

 * Helper function to query RAS EEPROM address

 *

 * @adev: amdgpu_device pointer

/**

 * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS

 * adev: amdgpu_device pointer

 * i2c_address: pointer to u8; if not NULL, will contain

 *    the RAS EEPROM address if the function returns true

 *

 * Return true if vbios supports ras rom address reporting

 * Return true if VBIOS supports RAS EEPROM address reporting,

 * else return false. If true and @i2c_address is not NULL,

 * will contain the RAS ROM address.

 */

bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, uint8_t* i2c_address)

bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,

				      u8 *i2c_address)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	int index;
@@ -483,26 +487,38 @@ bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev, uint8_t* i2c_a 
	union firmware_info *firmware_info;

	u8 frev, crev;



	if (i2c_address == NULL)

		return false;



	*i2c_address = 0;



	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,

					    firmwareinfo);



	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,

				index, &size, &frev, &crev, &data_offset)) {

					  index, &size, &frev, &crev,

					  &data_offset)) {

		/* support firmware_info 3.4 + */

		if ((frev == 3 && crev >=4) || (frev > 3)) {

			firmware_info = (union firmware_info *)

				(mode_info->atom_context->bios + data_offset);

			/* The ras_rom_i2c_slave_addr should ideally

			 * be a 19-bit EEPROM address, which would be

			 * used as is by the driver; see top of

			 * amdgpu_eeprom.c.

			 *

			 * When this is the case, 0 is of course a

			 * valid RAS EEPROM address, in which case,

			 * we'll drop the first "if (firm...)" and only

			 * leave the check for the pointer.

			 *

			 * The reason this works right now is because

			 * ras_rom_i2c_slave_addr contains the EEPROM

			 * device type qualifier 1010b in the top 4

			 * bits.

			 */

			if (firmware_info->v34.ras_rom_i2c_slave_addr) {

				if (i2c_address)

					*i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;

				return true;

			}

		}

	}



	if (*i2c_address != 0)

		return true;



	return false;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+1 −0
Original line number Diff line number Diff line
@@ -522,6 +522,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 
			break;

		case CHIP_RENOIR:

		case CHIP_VANGOGH:

		case CHIP_YELLOW_CARP:

			domain |= AMDGPU_GEM_DOMAIN_GTT;

			break;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+17 −0
Original line number Diff line number Diff line
@@ -1181,7 +1181,12 @@ static const struct pci_device_id pciidlist[] = { 
	{0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},

	{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
@@ -1197,6 +1202,11 @@ static const struct pci_device_id pciidlist[] = { 
	{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

	{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

	{0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

	{0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

	{0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

	{0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

	{0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

	{0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

	{0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},



	/* DIMGREY_CAVEFISH */
@@ -1204,6 +1214,13 @@ static const struct pci_device_id pciidlist[] = { 
	{0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},

	{0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},



	/* Aldebaran */

drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c

+9 −2
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ void amdgpu_show_fdinfo(struct seq_file *m, struct file *f) 
	uint64_t vram_mem = 0, gtt_mem = 0, cpu_mem = 0;

	struct drm_file *file = f->private_data;

	struct amdgpu_device *adev = drm_to_adev(file->minor->dev);

	struct amdgpu_bo *root;

	int ret;



	ret = amdgpu_file_to_fpriv(f, &fpriv);
@@ -69,13 +70,19 @@ void amdgpu_show_fdinfo(struct seq_file *m, struct file *f) 
	dev = PCI_SLOT(adev->pdev->devfn);

	fn = PCI_FUNC(adev->pdev->devfn);



	ret = amdgpu_bo_reserve(fpriv->vm.root.bo, false);

	root = amdgpu_bo_ref(fpriv->vm.root.bo);

	if (!root)

		return;



	ret = amdgpu_bo_reserve(root, false);

	if (ret) {

		DRM_ERROR("Fail to reserve bo\n");

		return;

	}

	amdgpu_vm_get_memory(&fpriv->vm, &vram_mem, &gtt_mem, &cpu_mem);

	amdgpu_bo_unreserve(fpriv->vm.root.bo);

	amdgpu_bo_unreserve(root);

	amdgpu_bo_unref(&root);



	seq_printf(m, "pdev:\t%04x:%02x:%02x.%d\npasid:\t%u\n", domain, bus,

			dev, fn, fpriv->vm.pasid);

	seq_printf(m, "vram mem:\t%llu kB\n", vram_mem/1024UL);

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+8 −0
Original line number Diff line number Diff line
@@ -552,6 +552,9 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev) 
		if (!ring || !ring->fence_drv.initialized)

			continue;



		if (!ring->no_scheduler)

			drm_sched_stop(&ring->sched, NULL);



		/* You can't wait for HW to signal if it's gone */

		if (!drm_dev_is_unplugged(&adev->ddev))

			r = amdgpu_fence_wait_empty(ring);
@@ -611,6 +614,11 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev) 
		if (!ring || !ring->fence_drv.initialized)

			continue;



		if (!ring->no_scheduler) {

			drm_sched_resubmit_jobs(&ring->sched);

			drm_sched_start(&ring->sched, true);

		}



		/* enable the interrupt */

		if (ring->fence_drv.irq_src)

			amdgpu_irq_get(adev, ring->fence_drv.irq_src,