Commit 069a11cc authored by Max.Tseng's avatar Max.Tseng Committed by Alex Deucher
Browse files

drm/amd/display: Add SE_DCN3_REG_LIST for control SDP num 



[Why] New platform. Need to add corresponding register control

Signed-off-by: default avatarMax.Tseng <Max.Tseng@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarWayne Lin <waynelin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 088bebc7

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h

+2 −0
Original line number Diff line number Diff line
@@ -85,7 +85,9 @@ 
	SRI(DP_MSE_RATE_UPDATE, DP, id), \

	SRI(DP_PIXEL_FORMAT, DP, id), \

	SRI(DP_SEC_CNTL, DP, id), \

	SRI(DP_SEC_CNTL1, DP, id), \

	SRI(DP_SEC_CNTL2, DP, id), \

	SRI(DP_SEC_CNTL5, DP, id), \

	SRI(DP_SEC_CNTL6, DP, id), \

	SRI(DP_STEER_FIFO, DP, id), \

	SRI(DP_VID_M, DP, id), \