Commit 066c3bd3 authored by Clément Léger's avatar Clément Léger Committed by David S. Miller
Browse files

ARM: dts: r9a06g032: describe MII converter 



Add the MII converter node which describes the MII converter that is
present on the RZ/N1 SoC.

Signed-off-by: default avatarClément Léger <clement.leger@bootlin.com>
Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d7cc14bc

arch/arm/boot/dts/r9a06g032.dtsi

+39 −0
Original line number Original line Diff line number Diff line
@@ -304,6 +304,45 @@ 
			data-width = <8>;

			data-width = <8>;

		};

		};





		eth_miic: eth-miic@44030000 {

			compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x44030000 0x10000>;

			clocks = <&sysctrl R9A06G032_CLK_MII_REF>,

				 <&sysctrl R9A06G032_CLK_RGMII_REF>,

				 <&sysctrl R9A06G032_CLK_RMII_REF>,

				 <&sysctrl R9A06G032_HCLK_SWITCH_RG>;

			clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";

			power-domains = <&sysctrl>;

			status = "disabled";



			mii_conv1: mii-conv@1 {

				reg = <1>;

				status = "disabled";

			};



			mii_conv2: mii-conv@2 {

				reg = <2>;

				status = "disabled";

			};



			mii_conv3: mii-conv@3 {

				reg = <3>;

				status = "disabled";

			};



			mii_conv4: mii-conv@4 {

				reg = <4>;

				status = "disabled";

			};



			mii_conv5: mii-conv@5 {

				reg = <5>;

				status = "disabled";

			};

		};



		gic: interrupt-controller@44101000 {

		gic: interrupt-controller@44101000 {

			compatible = "arm,gic-400", "arm,cortex-a7-gic";

			compatible = "arm,gic-400", "arm,cortex-a7-gic";

			interrupt-controller;

			interrupt-controller;