Commit 0662d797 authored by Ulf Hansson's avatar Ulf Hansson
Browse files

Merge branch 'fixes' into next

parents 95370684 3e5a8e84

drivers/mmc/host/sdhci-msm.c

+42 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <linux/regulator/consumer.h>

#include <linux/interconnect.h>

#include <linux/pinctrl/consumer.h>

#include <linux/reset.h>



#include "sdhci-pltfm.h"

#include "cqhci.h"
@@ -2507,6 +2508,43 @@ static inline void sdhci_msm_get_of_property(struct platform_device *pdev, 
	of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);

}



static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)

{

	struct reset_control *reset;

	int ret = 0;



	reset = reset_control_get_optional_exclusive(dev, NULL);

	if (IS_ERR(reset))

		return dev_err_probe(dev, PTR_ERR(reset),

				"unable to acquire core_reset\n");



	if (!reset)

		return ret;



	ret = reset_control_assert(reset);

	if (ret) {

		reset_control_put(reset);

		return dev_err_probe(dev, ret, "core_reset assert failed\n");

	}



	/*

	 * The hardware requirement for delay between assert/deassert

	 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to

	 * ~125us (4/32768). To be on the safe side add 200us delay.

	 */

	usleep_range(200, 210);



	ret = reset_control_deassert(reset);

	if (ret) {

		reset_control_put(reset);

		return dev_err_probe(dev, ret, "core_reset deassert failed\n");

	}



	usleep_range(200, 210);

	reset_control_put(reset);



	return ret;

}



static int sdhci_msm_probe(struct platform_device *pdev)

{
@@ -2554,6 +2592,10 @@ static int sdhci_msm_probe(struct platform_device *pdev) 


	msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;



	ret = sdhci_msm_gcc_reset(&pdev->dev, host);

	if (ret)

		goto pltfm_free;



	/* Setup SDCC bus voter clock. */

	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");

	if (!IS_ERR(msm_host->bus_clk)) {