Commit 06535a48 authored by Sung Lee's avatar Sung Lee Committed by Alex Deucher
Browse files

drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1 



[WHY]
In certain conditions with low pixel clock, some values in DML may go
past the max due to margining for latency hiding. This causes assertions
to get hit.

[HOW]
If the pixel clock is low and some values are high, cap it to the max.

Signed-off-by: default avatarSung Lee <sung.lee@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bccbf13d

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

+10 −2
Original line number Diff line number Diff line
@@ -1490,12 +1490,20 @@ static void dml_rq_dlg_get_dlg_params( 
	disp_dlg_regs->refcyc_per_pte_group_vblank_l =

			(unsigned int) (dst_y_per_row_vblank * (double) htotal

					* ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);

	if ((refclk_freq_in_mhz / ref_freq_to_pix_freq < 28) &&

			disp_dlg_regs->refcyc_per_pte_group_vblank_l >= (unsigned int)dml_pow(2, 13))

		disp_dlg_regs->refcyc_per_pte_group_vblank_l = (1 << 13) - 1;

	else

		ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));



	if (dual_plane) {

		disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank

				* (double) htotal * ref_freq_to_pix_freq

				/ (double) dpte_groups_per_row_ub_c);

		if ((refclk_freq_in_mhz / ref_freq_to_pix_freq < 28) &&

				disp_dlg_regs->refcyc_per_pte_group_vblank_c >= (unsigned int)dml_pow(2, 13))

			disp_dlg_regs->refcyc_per_pte_group_vblank_c = (1 << 13) - 1;

		else

			ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c

				< (unsigned int)dml_pow(2, 13));

	}