Commit 0602d593 authored by Suraj Kandpal's avatar Suraj Kandpal Committed by Animesh Manna
Browse files

drm/i915/display: Increase AUX timeout for Type-C 



Type-C PHYs are taking longer than expected for Aux IO Power Enabling.
Workaround: Increase the timeout.

---v2
-change style on how we mention WA [Ankit]
-fix bat error by creating new func that is only called for aux power
well scenarios so we can avoid null pointer error as it is called
everywhere.

--v3
-Add non-default enable_timeout to power well descriptor which avoids
adding more platform checks [Imre]

--v4
-Remove Bspec link from top to bottom remove WA link from commit put it
on comment [Jani]
-enable_timeout in ms and add .fixed_enable_delay too [Imre]

--v5
-move power_wells instead of duplicating them [Imre]

Bspec: 55480

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230418131425.1285088-1-suraj.kandpal@intel.com
parent bddc1891

drivers/gpu/drm/i915/display/intel_display_power_map.c

+7 −0
Original line number Diff line number Diff line
@@ -1387,6 +1387,11 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = { 
			I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),

			I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),

			I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),

		),

		.ops = &icl_aux_power_well_ops,

		.fixed_enable_delay = true,

	}, {

		.instances = &I915_PW_INSTANCES(

			I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),

			I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),

			I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
@@ -1394,6 +1399,8 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = { 
		),

		.ops = &icl_aux_power_well_ops,

		.fixed_enable_delay = true,

		/* WA_14017248603: adlp */

		.enable_timeout = 500,

	}, {

		.instances = &I915_PW_INSTANCES(

			I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),

drivers/gpu/drm/i915/display/intel_display_power_well.c

+2 −1
Original line number Diff line number Diff line
@@ -254,6 +254,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 
{

	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;

	int pw_idx = i915_power_well_instance(power_well)->hsw.idx;

	int timeout = power_well->desc->enable_timeout ? : 1;



	/*

	 * For some power wells we're not supposed to watch the status bit for
@@ -267,7 +268,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 


	/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */

	if (intel_de_wait_for_set(dev_priv, regs->driver,

				  HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {

				  HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) {

		drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",

			    intel_power_well_name(power_well));

drivers/gpu/drm/i915/display/intel_display_power_well.h

+2 −0
Original line number Diff line number Diff line
@@ -110,6 +110,8 @@ struct i915_power_well_desc { 
	 * Thunderbolt mode.

	 */

	u16 is_tc_tbt:1;

	/* Enable timeout if greater than the default 1ms */

	u16 enable_timeout;

};



struct i915_power_well {