Commit 0601a348 authored by Luoyouming's avatar Luoyouming Committed by Juan Zhou
Browse files

RDMA/hns: Fix mis-modifying default congestion control algorithm 

maillist inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I95UWO
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d20a7cf9f714f0763efb56f0f2eeca1cb91315ed



----------------------------------------------------------------------

Commit 27c5fd271d8b ("RDMA/hns: The UD mode can only be configured
with DCQCN") adds a check of congest control alorithm for UD. But
that patch causes a problem: hr_dev->caps.congest_type is global,
used by all QPs, so modifying this field to DCQCN for UD QPs causes
other QPs unable to use any other algorithm except DCQCN.

Revert the modification in commit 27c5fd271d8b ("RDMA/hns: The UD
mode can only be configured with DCQCN"). Add a new field cong_type
to struct hns_roce_qp and configure DCQCN for UD QPs.

Fixes: 27c5fd271d8b ("RDMA/hns: The UD mode can only be configured with DCQCN")
Fixes: f91696f2 ("RDMA/hns: Support congestion control type selection according to the FW")
Signed-off-by: default avatarLuoyouming <luoyouming@huawei.com>
Signed-off-by: default avatarJunxian Huang <huangjunxian6@hisilicon.com>
Link: https://lore.kernel.org/r/20240219061805.668170-1-huangjunxian6@hisilicon.com


Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
Signed-off-by: default avatarJuan Zhou <zhoujuan51@h-partners.com>
parent 40f699bc

drivers/infiniband/hw/hns/hns_roce_device.h

+9 −8
Original line number Diff line number Diff line
@@ -594,6 +594,13 @@ struct hns_roce_work { 
	u32 queue_num;

};



enum hns_roce_cong_type {

	CONG_TYPE_DCQCN,

	CONG_TYPE_LDCP,

	CONG_TYPE_HC3,

	CONG_TYPE_DIP,

};



struct hns_roce_qp {

	struct ib_qp		ibqp;

	struct hns_roce_wq	rq;
@@ -639,6 +646,7 @@ struct hns_roce_qp { 
	u32			config;

	u8			tc_mode;

	u8			priority;

	enum hns_roce_cong_type cong_type;

};



struct hns_roce_ib_iboe {
@@ -719,13 +727,6 @@ enum hns_roce_scc_algo { 
	HNS_ROCE_SCC_ALGO_TOTAL,

};



enum cong_type {

	CONG_TYPE_DCQCN,

	CONG_TYPE_LDCP,

	CONG_TYPE_HC3,

	CONG_TYPE_DIP,

};



struct hns_roce_caps {

	u64		fw_ver;

	u8		num_ports;
@@ -855,7 +856,7 @@ struct hns_roce_caps { 
	u16		default_aeq_period;

	u16		default_aeq_arm_st;

	u16		default_ceq_arm_st;

	enum cong_type	cong_type;

	enum hns_roce_cong_type cong_type;

};



enum hns_roce_device_state {

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+10 −6
Original line number Diff line number Diff line
@@ -4738,12 +4738,15 @@ static int check_cong_type(struct ib_qp *ibqp, 
			   struct hns_roce_congestion_algorithm *cong_alg)

{

	struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);

	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);



	if (ibqp->qp_type == IB_QPT_UD)

		hr_dev->caps.cong_type = CONG_TYPE_DCQCN;

	if (ibqp->qp_type == IB_QPT_UD || ibqp->qp_type == IB_QPT_GSI)

		hr_qp->cong_type = CONG_TYPE_DCQCN;

	else

		hr_qp->cong_type = hr_dev->caps.cong_type;



	/* different congestion types match different configurations */

	switch (hr_dev->caps.cong_type) {

	switch (hr_qp->cong_type) {

	case CONG_TYPE_DCQCN:

		cong_alg->alg_sel = CONG_DCQCN;

		cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;
@@ -4771,8 +4774,8 @@ static int check_cong_type(struct ib_qp *ibqp, 
	default:

		ibdev_warn(&hr_dev->ib_dev,

			   "invalid type(%u) for congestion selection.\n",

			   hr_dev->caps.cong_type);

		hr_dev->caps.cong_type = CONG_TYPE_DCQCN;

			   hr_qp->cong_type);

		hr_qp->cong_type = CONG_TYPE_DCQCN;

		cong_alg->alg_sel = CONG_DCQCN;

		cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL;

		cong_alg->dip_vld = DIP_INVALID;
@@ -4791,6 +4794,7 @@ static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 
	struct hns_roce_congestion_algorithm cong_field;

	struct ib_device *ibdev = ibqp->device;

	struct hns_roce_dev *hr_dev = to_hr_dev(ibdev);

	struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);

	u32 dip_idx = 0;

	int ret;
@@ -4803,7 +4807,7 @@ static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 
		return ret;



	hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id +

		     hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE);

		     hr_qp->cong_type * HNS_ROCE_CONG_SIZE);

	hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID);

	hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel);

	hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL);