Unverified Commit 05e8c95f authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!270 Synchronize the coresight code of the Linux mainline to support HiSilicon tracing 

Merge Pull Request from: @hejunhao3 
 

Synchronize the coresight code of the Linux mainline to support HiSilicon tracing

[Testing]
kernel config
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m
CONFIG_CORESIGHT_TRBE=m

[test log]
```shell
insmod coresight.ko coresight-etm4x.ko coresight-funnel.ko coresight-tmc.ko
estuary:/$ ls /sys/bus/coresight/devices/
ete0      ete12     ete2      ete6      funnel0   tmc_etf0  tmc_etr0
ete1      ete13     ete3      ete7      funnel1   tmc_etf1
ete10     ete14     ete4      ete8      funnel2   tmc_etf2
ete11     ete15     ete5      ete9      funnel3   tmc_etf3
estuary:/$ echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink
estuary:/$ echo 1 > /sys/bus/coresight/devices/ete3/enable_source
estuary:/$ cat /sys/bus/coresight/devices/tmc_etr0/mgmt/rwp
0x79100000
estuary:/$ cat /sys/bus/coresight/devices/tmc_etr0/mgmt/rwp
0x79106e00
estuary:/$ echo 0 > /sys/bus/coresight/devices/ete3/enable_source
estuary:/$ insmod /lib/modules/5.10.0+/ram_blk_drv.ko p_addr=0x79100000 p_size=0x3000
estuary:/$ dd if=/dev/ramblock  of=sys_c1_range.data bs=4k count=48
3+0 records in
3+0 records out
12288 bytes (12.0KB) copied, 0.028941 seconds, 414.6KB/s
estuary:/$ ptm2human -e -i sys_c1_range.data >sys_c1_range.data.log 2>&1
estuary:/$ grep sys_c1_range.data.log | "Decode trace stream of ID"
[22;1HDecode trace stream of ID 21
estuary:/$ 
estuary:/$ perf record -e /cs_etm/@tmc_etr0/ -C 7 taskset -c 7 uname -a
Linux (none) 5.10.0+ #3 SMP Thu Oct 27 14:51:05 CST 2022 aarch64 GNU/Linux
[ 2900.563565][  T306] coresight tmc_etr0: timeout while waiting for completion of Manual Flush
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.588 MB perf.data ]
estuary:/$ perf report --stdio -D > report.txt
estuary:/$ grep -rn "I_ASYNC : Alignment Synchronisation" report.txt
4244:	Idx:0; ID:1e;	I_ASYNC : Alignment Synchronisation.
6913:	Idx:4429; ID:1e;	I_ASYNC : Alignment Synchronisation.
9279:	Idx:8833; ID:1e;	I_ASYNC : Alignment Synchronisation.
``` 
 
Link:https://gitee.com/openeuler/kernel/pulls/270

 
Reviewed-by: default avatarLing Mingqiang <lingmingqiang@huawei.com>
Reviewed-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 1b709179 a4e207c2

Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x

+8 −0
Original line number Diff line number Diff line
@@ -371,6 +371,14 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 
Description:	(Read) Print the content of the Device ID Register

		(0xFC8).  The value is taken directly from the HW.



What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevarch

Date:		January 2021

KernelVersion:	5.12

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>

Description:	(Read) Print the content of the Device Architecture Register

		(offset 0xFBC).  The value is taken directly read

		from the HW.



What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype

Date:		April 2015

KernelVersion:	4.01

arch/arm64/configs/openeuler_defconfig

+2 −2
Original line number Diff line number Diff line
@@ -7252,7 +7252,7 @@ CONFIG_IO_STRICT_DEVMEM=y 
# CONFIG_ARM64_RELOC_TEST is not set

CONFIG_CORESIGHT=m

CONFIG_CORESIGHT_LINKS_AND_SINKS=m

# CONFIG_CORESIGHT_LINK_AND_SINK_TMC is not set

CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m

# CONFIG_CORESIGHT_SINK_TPIU is not set

# CONFIG_CORESIGHT_SINK_ETBV10 is not set

CONFIG_CORESIGHT_SOURCE_ETM4X=m
@@ -7260,7 +7260,7 @@ CONFIG_ETM4X_IMPDEF_FEATURE=y 
# CONFIG_CORESIGHT_STM is not set

# CONFIG_CORESIGHT_CPU_DEBUG is not set

# CONFIG_CORESIGHT_CTI is not set

# CONFIG_CORESIGHT_TRBE is not set

CONFIG_CORESIGHT_TRBE=m

CONFIG_ULTRASOC_SMB=m

# end of arm64 Debugging

arch/arm64/include/asm/barrier.h

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#define dsb(opt)	asm volatile("dsb " #opt : : : "memory")



#define psb_csync()	asm volatile("hint #17" : : : "memory")

#define tsb_csync()	asm volatile("hint #18" : : : "memory")

#define csdb()		asm volatile("hint #20" : : : "memory")



/*

arch/arm64/include/asm/sysreg.h

+61 −0
Original line number Diff line number Diff line
@@ -192,6 +192,7 @@ 
#define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)



#define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)

#define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)



#define SYS_TTBR0_EL1			sys_reg(3, 0, 2, 0, 0)

#define SYS_TTBR1_EL1			sys_reg(3, 0, 2, 0, 1)
@@ -333,6 +334,55 @@ 


/*** End of Statistical Profiling Extension ***/



/*

 * TRBE Registers

 */

#define SYS_TRBLIMITR_EL1		sys_reg(3, 0, 9, 11, 0)

#define SYS_TRBPTR_EL1			sys_reg(3, 0, 9, 11, 1)

#define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)

#define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)

#define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)

#define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)

#define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)



#define TRBLIMITR_LIMIT_MASK		GENMASK_ULL(51, 0)

#define TRBLIMITR_LIMIT_SHIFT		12

#define TRBLIMITR_NVM			BIT(5)

#define TRBLIMITR_TRIG_MODE_MASK	GENMASK(1, 0)

#define TRBLIMITR_TRIG_MODE_SHIFT	3

#define TRBLIMITR_FILL_MODE_MASK	GENMASK(1, 0)

#define TRBLIMITR_FILL_MODE_SHIFT	1

#define TRBLIMITR_ENABLE		BIT(0)

#define TRBPTR_PTR_MASK			GENMASK_ULL(63, 0)

#define TRBPTR_PTR_SHIFT		0

#define TRBBASER_BASE_MASK		GENMASK_ULL(51, 0)

#define TRBBASER_BASE_SHIFT		12

#define TRBSR_EC_MASK			GENMASK(5, 0)

#define TRBSR_EC_SHIFT			26

#define TRBSR_IRQ			BIT(22)

#define TRBSR_TRG			BIT(21)

#define TRBSR_WRAP			BIT(20)

#define TRBSR_ABORT			BIT(18)

#define TRBSR_STOP			BIT(17)

#define TRBSR_MSS_MASK			GENMASK(15, 0)

#define TRBSR_MSS_SHIFT			0

#define TRBSR_BSC_MASK			GENMASK(5, 0)

#define TRBSR_BSC_SHIFT			0

#define TRBSR_FSC_MASK			GENMASK(5, 0)

#define TRBSR_FSC_SHIFT			0

#define TRBMAR_SHARE_MASK		GENMASK(1, 0)

#define TRBMAR_SHARE_SHIFT		8

#define TRBMAR_OUTER_MASK		GENMASK(3, 0)

#define TRBMAR_OUTER_SHIFT		4

#define TRBMAR_INNER_MASK		GENMASK(3, 0)

#define TRBMAR_INNER_SHIFT		0

#define TRBTRG_TRG_MASK			GENMASK(31, 0)

#define TRBTRG_TRG_SHIFT		0

#define TRBIDR_FLAG			BIT(5)

#define TRBIDR_PROG			BIT(4)

#define TRBIDR_ALIGN_MASK		GENMASK(3, 0)

#define TRBIDR_ALIGN_SHIFT		0



#define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)

#define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
@@ -478,6 +528,7 @@ 
#define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)



#define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)

#define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)

#define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)

#define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)

#define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
@@ -855,6 +906,8 @@ 
#define ID_AA64MMFR2_CNP_SHIFT		0



/* id_aa64dfr0 */

#define ID_AA64DFR0_TRBE_SHIFT		44

#define ID_AA64DFR0_TRACE_FILT_SHIFT	40

#define ID_AA64DFR0_DOUBLELOCK_SHIFT	36

#define ID_AA64DFR0_PMSVER_SHIFT	32

#define ID_AA64DFR0_CTX_CMPS_SHIFT	28
@@ -1032,6 +1085,14 @@ 
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */

#define SYS_MPIDR_SAFE_VAL	(BIT(31))



#define TRFCR_ELx_TS_SHIFT		5

#define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)

#define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)

#define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)

#define TRFCR_EL2_CX			BIT(3)

#define TRFCR_ELx_ExTRE			BIT(1)

#define TRFCR_ELx_E0TRE			BIT(0)



#ifdef __ASSEMBLY__



	.irp	num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30

arch/arm64/kvm/sys_regs.c

+1 −0
Original line number Diff line number Diff line
@@ -1573,6 +1573,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	{ SYS_DESC(SYS_GCR_EL1), undef_access },



	{ SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },

	{ SYS_DESC(SYS_TRFCR_EL1), undef_access },

	{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },

	{ SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },

	{ SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },