Commit 05c44ed0 authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo
Browse files

ARM: dts: imx6ull: add TQ-Systems MBa6ULLx device trees 



Add device trees for the MBa6ULx mainboard with TQMa6ULLx SoMs.

Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent a333f3e4

arch/arm/boot/dts/Makefile

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@@ -713,6 +713,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ 
	imx6ull-phytec-segin-ff-rdk-nand.dtb \

	imx6ull-phytec-segin-ff-rdk-emmc.dtb \

	imx6ull-phytec-segin-lc-rdk-nand.dtb \

	imx6ull-tqma6ull2-mba6ulx.dtb \

	imx6ulz-14x14-evk.dtb \

	imx6ulz-bsh-smm-m2.dtb

dtb-$(CONFIG_SOC_IMX7D) += \

arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts

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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)

/*

 * Copyright 2018-2022 TQ-Systems GmbH

 * Author: Markus Niebel <Markus.Niebel@tq-group.com>

 */



/dts-v1/;



#include "imx6ull-tqma6ull2.dtsi"

#include "mba6ulx.dtsi"



/ {

	model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board";

	compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull";

};

arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi

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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)

/*

 * Copyright 2018-2022 TQ-Systems GmbH

 * Author: Markus Niebel <Markus.Niebel@tq-group.com>

 */



#include "imx6ull.dtsi"

#include "imx6ul-tqma6ul-common.dtsi"

#include "imx6ul-tqma6ulx-common.dtsi"



/ {

	model = "TQ-Systems TQMa6ULL2 SoM";

	compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";

};



&usdhc2 {

	fsl,tuning-step= <6>;

	/* Errata ERR010450 Workaround */

	max-frequency = <99000000>;

	assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;

	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;

	assigned-clock-rates = <0>, <198000000>;

};



&iomuxc {

	pinctrl_usdhc2: usdhc2grp {

		fsl,pins = <

			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x00017031

			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x00017039

			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x00017039

			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x00017039

			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x00017039

			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x00017039

			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x00017039

			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x00017039

			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x00017039

			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x00017039

			/* rst */

			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051

		>;

	};



	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

		fsl,pins = <

			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x000170f1

			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x000170f1

			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x000170f1

			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x000170f1

			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x000170f1

			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x000170f1

			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x000170f1

			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x000170f1

			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x000170f1

			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x000170f1

			/* rst */

			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051

		>;

	};



	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {

		fsl,pins = <

			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x000170f1

			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x000170f1

			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x000170f1

			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x000170f1

			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x000170f1

			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x000170f1

			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x000170f1

			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x000170f1

			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x000170f1

			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x000170f1

			/* rst */

			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051

		>;

	};

};