Commit 057f4af2 authored by Gatis Peisenieks's avatar Gatis Peisenieks Committed by Jakub Kicinski
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atl1c: add 4 RX/TX queue support for Mikrotik 10/25G NIC 



More RX/TX queues on a network card help spread the CPU load among
cores and achieve higher overall networking performance. The new
Mikrotik 10/25G NIC supports 4 RX and 4 TX queues. TX queues are
treated with equal priority. RX queue balancing is fixed based on
L2/L3/L4 hash.

This adds support for 4 RX/TX queues while maintaining backwards
compatibility with older hardware.

Simultaneous TX + RX performance on AMD Threadripper 3960X
with Mikrotik 10/25G NIC improved from 1.6Mpps to 3.2Mpps per port.

Backwards compatiblitiy was verified with AR8151 and AR8131 based
NICs.

Signed-off-by: default avatarGatis Peisenieks <gatis@mikrotik.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 8042824a

drivers/net/ethernet/atheros/atl1c/atl1c.h

+3 −6
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ 


#define AT_MAX_RECEIVE_QUEUE    4

#define AT_DEF_RECEIVE_QUEUE	1

#define AT_MAX_TRANSMIT_QUEUE	2

#define AT_MAX_TRANSMIT_QUEUE  4



#define AT_DMA_HI_ADDR_MASK     0xffffffff00000000ULL

#define AT_DMA_LO_ADDR_MASK     0x00000000ffffffffULL
@@ -294,11 +294,6 @@ enum atl1c_nic_type { 
	athr_mt,

};



enum atl1c_trans_queue {

	atl1c_trans_normal = 0,

	atl1c_trans_high = 1

};



struct atl1c_hw_stats {

	/* rx */

	unsigned long rx_ok;		/* The number of good packet received. */
@@ -522,6 +517,8 @@ struct atl1c_adapter { 
	struct atl1c_hw_stats  hw_stats;

	struct mii_if_info  mii;    /* MII interface info */

	u16 rx_buffer_len;

	unsigned int tx_queue_count;

	unsigned int rx_queue_count;



	unsigned long flags;

#define __AT_TESTING        0x0001

drivers/net/ethernet/atheros/atl1c/atl1c_hw.h

+31 −3
Original line number Diff line number Diff line
@@ -528,15 +528,24 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); 
#define REG_RX_BASE_ADDR_HI		0x1540

#define REG_TX_BASE_ADDR_HI		0x1544

#define REG_RFD0_HEAD_ADDR_LO		0x1550

#define REG_RFD1_HEAD_ADDR_LO          0x1554

#define REG_RFD2_HEAD_ADDR_LO          0x1558

#define REG_RFD3_HEAD_ADDR_LO          0x155C

#define REG_RFD_RING_SIZE		0x1560

#define RFD_RING_SIZE_MASK		0x0FFF

#define REG_RX_BUF_SIZE			0x1564

#define RX_BUF_SIZE_MASK		0xFFFF

#define REG_RRD0_HEAD_ADDR_LO		0x1568

#define REG_RRD1_HEAD_ADDR_LO          0x156C

#define REG_RRD2_HEAD_ADDR_LO          0x1570

#define REG_RRD3_HEAD_ADDR_LO          0x1574

#define REG_RRD_RING_SIZE		0x1578

#define RRD_RING_SIZE_MASK		0x0FFF

#define REG_TPD_PRI1_ADDR_LO		0x157C

#define REG_TPD_PRI0_ADDR_LO		0x1580

#define REG_TPD_PRI2_ADDR_LO           0x1F10

#define REG_TPD_PRI3_ADDR_LO           0x1F14



#define REG_TPD_RING_SIZE		0x1584

#define TPD_RING_SIZE_MASK		0xFFFF
@@ -655,15 +664,26 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); 
/* Mail box */

#define MB_RFDX_PROD_IDX_MASK		0xFFFF

#define REG_MB_RFD0_PROD_IDX		0x15E0

#define REG_MB_RFD1_PROD_IDX           0x15E4

#define REG_MB_RFD2_PROD_IDX           0x15E8

#define REG_MB_RFD3_PROD_IDX           0x15EC



#define REG_TPD_PRI1_PIDX               0x15F0	/* 16bit,hi-tpd producer idx */

#define REG_TPD_PRI0_PIDX		0x15F2	/* 16bit,lo-tpd producer idx */

#define REG_TPD_PRI1_CIDX		0x15F4	/* 16bit,hi-tpd consumer idx */

#define REG_TPD_PRI0_CIDX		0x15F6	/* 16bit,lo-tpd consumer idx */

#define REG_TPD_PRI3_PIDX              0x1F18

#define REG_TPD_PRI2_PIDX              0x1F1A

#define REG_TPD_PRI3_CIDX              0x1F1C

#define REG_TPD_PRI2_CIDX              0x1F1E





#define REG_MB_RFD01_CONS_IDX		0x15F8

#define MB_RFD0_CONS_IDX_MASK		0x0000FFFF

#define MB_RFD1_CONS_IDX_MASK		0xFFFF0000

#define REG_MB_RFD23_CONS_IDX          0x15FC

#define MB_RFD2_CONS_IDX_MASK          0x0000FFFF

#define MB_RFD3_CONS_IDX_MASK          0xFFFF0000



/* Interrupt Status Register */

#define REG_ISR    			0x1600
@@ -687,7 +707,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); 
/* GPHY low power state interrupt */

#define ISR_GPHY_LPW           		0x00002000

#define ISR_TXQ_TO_RST			0x00004000

#define ISR_TX_PKT			0x00008000

#define ISR_TX_PKT_0                   0x00008000

#define ISR_RX_PKT_0			0x00010000

#define ISR_RX_PKT_1			0x00020000

#define ISR_RX_PKT_2			0x00040000
@@ -699,6 +719,9 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); 
#define ISR_NFERR_DETECTED		0x01000000

#define ISR_CERR_DETECTED		0x02000000

#define ISR_PHY_LINKDOWN		0x04000000

#define ISR_TX_PKT_1                   0x10000000

#define ISR_TX_PKT_2                   0x20000000

#define ISR_TX_PKT_3                   0x40000000

#define ISR_DIS_INT			0x80000000



/* Interrupt Mask Register */
@@ -713,11 +736,15 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); 
		ISR_TXQ_TO_RST  |\

		ISR_DMAW_TO_RST	|\

		ISR_GPHY	|\

		ISR_TX_PKT	|\

		ISR_RX_PKT_0	|\

		ISR_GPHY_LPW    |\

		ISR_PHY_LINKDOWN)



#define ISR_TX_PKT     (			\

	ISR_TX_PKT_0    |			\

	ISR_TX_PKT_1    |			\

	ISR_TX_PKT_2    |			\

	ISR_TX_PKT_3)



#define ISR_RX_PKT 	(\

	ISR_RX_PKT_0    |\

	ISR_RX_PKT_1    |\
@@ -771,6 +798,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); 
#define REG_MT_VERSION			0x1F0C



#define MT_MAGIC			0xaabb1234

#define MT_MODE_4Q			BIT(0)



#define L1D_MPW_PHYID1			0xD01C  /* V7 */

#define L1D_MPW_PHYID2			0xD01D  /* V1-V6 */

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

+257 −149

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