Commit 05593a3f authored by William Breathitt Gray's avatar William Breathitt Gray Committed by Jonathan Cameron
Browse files

counter: stm32-lptimer-cnt: Provide defines for clock polarities 



The STM32 low-power timer permits configuration of the clock polarity
via the LPTIMX_CFGR register CKPOL bits. This patch provides
preprocessor defines for the supported clock polarities.

Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: default avatarWilliam Breathitt Gray <vilhelm.gray@gmail.com>
Reviewed-by: default avatarFabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/a111c8905c467805ca530728f88189b59430f27e.1630031207.git.vilhelm.gray@gmail.com


Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent 6880fa6c

drivers/counter/stm32-lptimer-cnt.c

+3 −3
Original line number Diff line number Diff line
@@ -140,9 +140,9 @@ static const enum counter_function stm32_lptim_cnt_functions[] = { 
};



enum stm32_lptim_synapse_action {

	STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,

	STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,

	STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,

	STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE = STM32_LPTIM_CKPOL_RISING_EDGE,

	STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE = STM32_LPTIM_CKPOL_FALLING_EDGE,

	STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES = STM32_LPTIM_CKPOL_BOTH_EDGES,

	STM32_LPTIM_SYNAPSE_ACTION_NONE,

};

include/linux/mfd/stm32-lptimer.h

+5 −0
Original line number Diff line number Diff line
@@ -45,6 +45,11 @@ 
#define STM32_LPTIM_PRESC	GENMASK(11, 9)

#define STM32_LPTIM_CKPOL	GENMASK(2, 1)



/* STM32_LPTIM_CKPOL */

#define STM32_LPTIM_CKPOL_RISING_EDGE	0

#define STM32_LPTIM_CKPOL_FALLING_EDGE	1

#define STM32_LPTIM_CKPOL_BOTH_EDGES	2



/* STM32_LPTIM_ARR */

#define STM32_LPTIM_MAX_ARR	0xFFFF