Commit 0541e021 authored by Rajan Vaja's avatar Rajan Vaja Committed by Stephen Boyd
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clk: zynqmp: Limit bestdiv with maxdiv 



Clock divider value should not be greater than maximum divider value.
So use minimum of best divider or maximum divider value.

Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: default avatarJolly Shah <jolly.shah@xilinx.com>
Link: https://lkml.kernel.org/r/1583185843-20707-2-git-send-email-jolly.shah@xilinx.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 8f3d9f35

drivers/clk/zynqmp/divider.c

+2 −0
Original line number Diff line number Diff line
@@ -197,6 +197,8 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, 


	if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)

		bestdiv = rate % *prate ? 1 : bestdiv;



	bestdiv = min_t(u32, bestdiv, divider->max_div);

	*prate = rate * bestdiv;



	return rate;