Commit 04fb918b authored by Ilya Bakoulin's avatar Ilya Bakoulin Committed by Alex Deucher
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drm/amd/display: Fix pixel clock programming 



[Why]
Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned
between different HDMI lanes when using YCbCr420 10-bit pixel format.

BIOS functions for transmitter/encoder control take pixel clock in kHz
increments, whereas the function for setting the pixel clock is in 100Hz
increments. Setting pixel clock to a value that is not on a kHz boundary
will cause the issue.

[How]
Round pixel clock down to nearest kHz in 10/12-bpc cases.

Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarIlya Bakoulin <Ilya.Bakoulin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 84435d1d

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+2 −0
Original line number Diff line number Diff line
@@ -543,9 +543,11 @@ static void dce112_get_pix_clk_dividers_helper ( 
		switch (pix_clk_params->color_depth) {

		case COLOR_DEPTH_101010:

			actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2;

			actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;

			break;

		case COLOR_DEPTH_121212:

			actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2;

			actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;

			break;

		case COLOR_DEPTH_161616:

			actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2;