Unverified Commit 04ef6795 authored Jan 18, 2021 by Andre Przywara Committed by Maxime Ripard Jan 20, 2021

clk: sunxi-ng: h6: Fix clock divider range on some clocks

While comparing clocks between the H6 and H616, some of the M factor
ranges were found to be wrong: the manual says they are only covering
two bits [1:0], but our code had "5" in the number-of-bits field.

By writing 0xff into that register in U-Boot and via FEL, it could be
confirmed that bits [4:2] are indeed masked off, so the manual is right.

Change to number of bits in the affected clock's description.

Fixes: 524353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210118000912.28116-1-andre.przywara@arm.com

parent eec9d9b7

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -237,7 +237,7 @@ static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
		static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
		psi_ahb1_ahb2_parents,
		0x510,
		0, 5, /* M */
		0, 2, /* M */
		8, 2, /* P */
		24, 2, /* mux */
		0);
		@@ -246,19 +246,19 @@ static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
		"psi-ahb1-ahb2",
		"pll-periph0" };
		static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
		0, 5, /* M */
		0, 2, /* M */
		8, 2, /* P */
		24, 2, /* mux */
		0);

		static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
		0, 5, /* M */
		0, 2, /* M */
		8, 2, /* P */
		24, 2, /* mux */
		0);

		static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
		0, 5, /* M */
		0, 2, /* M */
		8, 2, /* P */
		24, 2, /* mux */
		0);