Commit 04eb6e77 authored by chen gong's avatar chen gong Committed by Alex Deucher
Browse files

drm/amdgpu/gfx10: add updated GOLDEN_TSC_COUNT_UPPER/LOWER register offsets for VGH 



The address of the GOLDEN_TSC_COUNT_UPPER/GOLDEN_TSC_COUNT_LOWER for
Vnagogh are different from the others.

The offset of the GOLDEN_TSC_COUNT_UPPER for Vangogh is 0x0025 by
calculation.
The offset of the GOLDEN_TSC_COUNT_LOWER for Vangogh is 0x0026 by
calculation.

Signed-off-by: default avatarchen gong <curry.gong@amd.com>
Acked-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8b335bff

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+14 −2
Original line number Diff line number Diff line
@@ -99,6 +99,10 @@ 
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580

#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0



#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025

#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1

#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026

#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1

#define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441

#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1

#define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
@@ -7377,8 +7381,16 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 


	amdgpu_gfx_off_ctrl(adev, false);

	mutex_lock(&adev->gfx.gpu_clock_mutex);

	switch (adev->asic_type) {

	case CHIP_VANGOGH:

		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |

			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);

		break;

	default:

		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |

			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);

		break;

	}

	mutex_unlock(&adev->gfx.gpu_clock_mutex);

	amdgpu_gfx_off_ctrl(adev, true);

	return clock;