Commit 04aa6437 authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Linus Torvalds
Browse files

drm/i915: fix TLB invalidation for Gen12 video and compute engines 



In case of Gen12 video and compute engines, TLB_INV registers are masked -
to modify one bit, corresponding bit in upper half of the register must
be enabled, otherwise nothing happens.

CVE: CVE-2022-4139
Suggested-by: default avatarChris Wilson <chris.p.wilson@intel.com>
Signed-off-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Fixes: 7938d615 ("drm/i915: Flush TLBs before releasing backing store")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 01f856ae

drivers/gpu/drm/i915/gt/intel_gt.c

+5 −0
Original line number Diff line number Diff line
@@ -1017,6 +1017,11 @@ static void mmio_invalidate_full(struct intel_gt *gt) 
		if (!i915_mmio_reg_offset(rb.reg))

			continue;



		if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||

		    engine->class == VIDEO_ENHANCEMENT_CLASS ||

		    engine->class == COMPUTE_CLASS))

			rb.bit = _MASKED_BIT_ENABLE(rb.bit);



		intel_uncore_write_fw(uncore, rb.reg, rb.bit);

		awake |= engine->mask;

	}