Commit 0434a406 authored by Rob Clark's avatar Rob Clark Committed by Rob Clark
Browse files

firmware: qcom: scm: add support to restore secure config to qcm_scm-32 



Add support to restore the secure configuration for qcm_scm-32.c. This
is needed by the On Chip MEMory (OCMEM) that is present on some
Snapdragon devices.

Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
[masneyb@onstation.org: ported to latest kernel; set ctx_bank_num to
 spare parameter.]
Signed-off-by: default avatarBrian Masney <masneyb@onstation.org>
Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Gabriel Francisco <frc.gabrielgmail.com>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent b0a1614f

drivers/firmware/qcom_scm-32.c

+16 −1
Original line number Diff line number Diff line
@@ -617,7 +617,22 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, 
int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,

			       u32 spare)

{

	return -ENODEV;

	struct msm_scm_sec_cfg {

		__le32 id;

		__le32 ctx_bank_num;

	} cfg;

	int ret, scm_ret = 0;



	cfg.id = cpu_to_le32(device_id);

	cfg.ctx_bank_num = cpu_to_le32(spare);



	ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_RESTORE_SEC_CFG,

			    &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));



	if (ret || scm_ret)

		return ret ? ret : -EINVAL;



	return 0;

}



int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,

drivers/firmware/qcom_scm.c

+13 −0
Original line number Diff line number Diff line
@@ -367,6 +367,19 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = { 
	.deassert = qcom_scm_pas_reset_deassert,

};



/**

 * qcom_scm_restore_sec_cfg_available() - Check if secure environment

 * supports restore security config interface.

 *

 * Return true if restore-cfg interface is supported, false if not.

 */

bool qcom_scm_restore_sec_cfg_available(void)

{

	return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,

					    QCOM_SCM_RESTORE_SEC_CFG);

}

EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);



int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)

{

	return __qcom_scm_restore_sec_cfg(__scm->dev, device_id, spare);

include/linux/qcom_scm.h

+11 −0
Original line number Diff line number Diff line
@@ -34,6 +34,16 @@ enum qcom_scm_ocmem_client { 
	QCOM_SCM_OCMEM_DEBUG_ID,

};



enum qcom_scm_sec_dev_id {

	QCOM_SCM_MDSS_DEV_ID    = 1,

	QCOM_SCM_OCMEM_DEV_ID   = 5,

	QCOM_SCM_PCIE0_DEV_ID   = 11,

	QCOM_SCM_PCIE1_DEV_ID   = 12,

	QCOM_SCM_GFX_DEV_ID     = 18,

	QCOM_SCM_UFS_DEV_ID     = 19,

	QCOM_SCM_ICE_DEV_ID     = 20,

};



#define QCOM_SCM_VMID_HLOS       0x3

#define QCOM_SCM_VMID_MSS_MSA    0xF

#define QCOM_SCM_VMID_WLAN       0x18
@@ -70,6 +80,7 @@ extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, 
extern void qcom_scm_cpu_power_down(u32 flags);

extern u32 qcom_scm_get_version(void);

extern int qcom_scm_set_remote_state(u32 state, u32 id);

extern bool qcom_scm_restore_sec_cfg_available(void);

extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);

extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);

extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);