Commit 042c0bd7 authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: dc: Parameterize maximum resolution



Tegra186 and later support a higher maximum resolution than earlier
chips, so make sure to reflect that in the mode configuration.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 86044e74
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+6 −0
Original line number Diff line number Diff line
@@ -2117,6 +2117,12 @@ static int tegra_dc_init(struct host1x_client *client)
	if (dc->soc->pitch_align > tegra->pitch_align)
		tegra->pitch_align = dc->soc->pitch_align;

	/* track maximum resolution */
	if (dc->soc->has_nvdisplay)
		drm->mode_config.max_width = drm->mode_config.max_height = 16384;
	else
		drm->mode_config.max_width = drm->mode_config.max_height = 4096;

	err = tegra_dc_rgb_init(drm, dc);
	if (err < 0 && err != -ENODEV) {
		dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
+10 −3
Original line number Diff line number Diff line
@@ -1121,9 +1121,8 @@ static int host1x_drm_probe(struct host1x_device *dev)

	drm->mode_config.min_width = 0;
	drm->mode_config.min_height = 0;

	drm->mode_config.max_width = 4096;
	drm->mode_config.max_height = 4096;
	drm->mode_config.max_width = 0;
	drm->mode_config.max_height = 0;

	drm->mode_config.allow_fb_modifiers = true;

@@ -1142,6 +1141,14 @@ static int host1x_drm_probe(struct host1x_device *dev)
	if (err < 0)
		goto fbdev;

	/*
	 * Now that all display controller have been initialized, the maximum
	 * supported resolution is known and the bitmask for horizontal and
	 * vertical bitfields can be computed.
	 */
	tegra->hmask = drm->mode_config.max_width - 1;
	tegra->vmask = drm->mode_config.max_height - 1;

	if (tegra->use_explicit_iommu) {
		u64 carveout_start, carveout_end, gem_start, gem_end;
		u64 dma_mask = dma_get_mask(&dev->dev);
+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ struct tegra_drm {
	struct tegra_fbdev *fbdev;
#endif

	unsigned int hmask, vmask;
	unsigned int pitch_align;

	struct tegra_display_hub *hub;