Commit 0422c34c authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: enable VCN RAS poison for VCN v4.0 



Configure related registers.

Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a6b3b618

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

+24 −0
Original line number Diff line number Diff line
@@ -862,6 +862,28 @@ static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 
	return;

}



static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,

				bool indirect)

{

	uint32_t tmp;



	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))

		return;



	tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |

	      VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |

	      VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |

	      VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;

	WREG32_SOC15_DPG_MODE(inst_idx,

			      SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),

			      tmp, 0, indirect);



	tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;

	WREG32_SOC15_DPG_MODE(inst_idx,

			      SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),

			      tmp, 0, indirect);

}



/**

 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode

 *
@@ -950,6 +972,8 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo 
	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);



	vcn_v4_0_enable_ras(adev, inst_idx, indirect);



	/* enable master interrupt */

	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

		VCN, inst_idx, regUVD_MASTINT_EN),