Commit 040184b7 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Stephen Boyd
Browse files

clk: qcom: gpucc-sdm845: convert to parent data 



Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-13-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 7acd2251

drivers/clk/qcom/gpucc-sdm845.c

+23 −21
Original line number Diff line number Diff line
@@ -33,22 +33,6 @@ enum { 
	P_GPU_CC_PLL1_OUT_MAIN,

};



static const struct parent_map gpu_cc_parent_map_0[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },

	{ P_GPLL0_OUT_MAIN, 5 },

	{ P_GPLL0_OUT_MAIN_DIV, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const gpu_cc_parent_names_0[] = {

	"bi_tcxo",

	"gpu_cc_pll1",

	"gcc_gpu_gpll0_clk_src",

	"gcc_gpu_gpll0_div_clk_src",

	"core_bi_pll_test_se",

};



static const struct alpha_pll_config gpu_cc_pll1_config = {

	.l = 0x1a,

	.alpha = 0xaab,
@@ -60,13 +44,31 @@ static struct clk_alpha_pll gpu_cc_pll1 = { 
	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_pll1",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.parent_data = &(const struct clk_parent_data){

				.fw_name = "bi_tcxo", .name = "bi_tcxo",

			},

			.num_parents = 1,

			.ops = &clk_alpha_pll_fabia_ops,

		},

	},

};



static const struct parent_map gpu_cc_parent_map_0[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },

	{ P_GPLL0_OUT_MAIN, 5 },

	{ P_GPLL0_OUT_MAIN_DIV, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gpu_cc_parent_data_0[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .hw = &gpu_cc_pll1.clkr.hw },

	{ .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },

	{ .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
@@ -82,8 +84,8 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { 
	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpu_cc_gmu_clk_src",

		.parent_names = gpu_cc_parent_names_0,

		.num_parents = 5,

		.parent_data = gpu_cc_parent_data_0,

		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),

		.ops = &clk_rcg2_shared_ops,

	},

};
@@ -96,8 +98,8 @@ static struct clk_branch gpu_cc_cx_gmu_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cx_gmu_clk",

			.parent_names = (const char *[]){

				"gpu_cc_gmu_clk_src",

			.parent_hws = (const struct clk_hw*[]){

				&gpu_cc_gmu_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,