Commit 03eababb authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: s/HAS_BAR2_SMEM_STOLEN/HAS_LMEMBAR_SMEM_STOLEN/



The fact that LMEMBAR is BAR2 should be of no real interest
to anyone. So use the name of the BAR rather than its index.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221005154159.18750-3-ville.syrjala@linux.intel.com


Acked-by: default avatarMatthew Auld <matthew.auld@intel.com>
parent 0492a34c
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+7 −7
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ void i915_gem_stolen_remove_node(struct drm_i915_private *i915,

static bool valid_stolen_size(struct drm_i915_private *i915, struct resource *dsm)
{
	return (dsm->start != 0 || HAS_BAR2_SMEM_STOLEN(i915)) && dsm->end > dsm->start;
	return (dsm->start != 0 || HAS_LMEMBAR_SMEM_STOLEN(i915)) && dsm->end > dsm->start;
}

static int adjust_stolen(struct drm_i915_private *i915,
@@ -151,9 +151,9 @@ static int request_smem_stolen(struct drm_i915_private *i915,
	 * address range since it's local to the gpu.
	 *
	 * Starting MTL, in IGFX devices the stolen memory is exposed via
	 * BAR2 and shall be considered similar to stolen lmem.
	 * LMEMBAR and shall be considered similar to stolen lmem.
	 */
	if (HAS_LMEM(i915) || HAS_BAR2_SMEM_STOLEN(i915))
	if (HAS_LMEM(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915))
		return 0;

	/*
@@ -406,7 +406,7 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
		MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
	}

	if (HAS_BAR2_SMEM_STOLEN(i915))
	if (HAS_LMEMBAR_SMEM_STOLEN(i915))
		/* the base is initialized to stolen top so subtract size to get base */
		*base -= *size;
	else
@@ -881,7 +881,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
	if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
		return ERR_PTR(-ENXIO);

	if (HAS_BAR2_SMEM_STOLEN(i915) || IS_DG1(i915)) {
	if (HAS_LMEMBAR_SMEM_STOLEN(i915) || IS_DG1(i915)) {
		lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
	} else {
		resource_size_t lmem_range;
@@ -891,7 +891,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
		lmem_size *= SZ_1G;
	}

	if (HAS_BAR2_SMEM_STOLEN(i915)) {
	if (HAS_LMEMBAR_SMEM_STOLEN(i915)) {
		/*
		 * MTL dsm size is in GGC register.
		 * Also MTL uses offset to DSMBASE in ptes, so i915
@@ -917,7 +917,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
	}

	io_size = dsm_size;
	if (HAS_BAR2_SMEM_STOLEN(i915)) {
	if (HAS_LMEMBAR_SMEM_STOLEN(i915)) {
		io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) + SZ_8M;
	} else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
		io_start = 0;
+1 −1
Original line number Diff line number Diff line
@@ -931,7 +931,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
	unsigned int size;
	u16 snb_gmch_ctl;

	if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) {
	if (!HAS_LMEM(i915) && !HAS_LMEMBAR_SMEM_STOLEN(i915)) {
		if (!i915_pci_resource_valid(pdev, GEN4_GMADR_BAR))
			return -ENXIO;

+2 −2
Original line number Diff line number Diff line
@@ -970,7 +970,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,

#define HAS_ONE_EU_PER_FUSE_BIT(i915)	(INTEL_INFO(i915)->has_one_eu_per_fuse_bit)

#define HAS_BAR2_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
				       GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))

/* intel_device_info.c */