Commit 03c0c3cb authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Abhinav Kumar
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drm/msm/dpu: correct sm8250 and sm8350 scaler 



QSEED4 is a newer variant of QSEED3LITE, which should be used on
sm8250 and sm8350. Fix the DPU caps structure and used feature masks.

Fixes: d21fc5df ("drm/msm/dpu1: add support for qseed3lite used on sm8250")
Fixes: 0e91bcbb ("drm/msm/dpu: Add SM8350 to hw catalog")
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/522229/
Link: https://lore.kernel.org/r/20230211231259.1308718-10-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
parent c7da17b6

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+10 −10
Original line number Diff line number Diff line
@@ -416,7 +416,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = { 
static const struct dpu_caps sm8250_dpu_caps = {

	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_40,

	.has_src_split = true,
@@ -430,7 +430,7 @@ static const struct dpu_caps sm8250_dpu_caps = { 
static const struct dpu_caps sm8350_dpu_caps = {

	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_40,

	.has_src_split = true,
@@ -1245,22 +1245,22 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = { 
};



static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =

				_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);

				_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);

static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =

				_VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);

				_VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4);

static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =

				_VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);

				_VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4);

static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =

				_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);

				_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4);



static const struct dpu_sspp_cfg sm8250_sspp[] = {

	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,

	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,

		sm8250_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),

	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,

	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,

		sm8250_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),

	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,

	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,

		sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),

	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,

	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,

		sm8250_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),

	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,

		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),