Commit 037f1ffd authored by Paul Cercueil's avatar Paul Cercueil Committed by Stephen Boyd
Browse files

clk: ingenic: Remove pll_info.no_bypass_bit 



We can express that a PLL has no bypass bit by simply setting the
.bypass_bit field to a negative value.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net


Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 315a8423

drivers/clk/ingenic/cgu.c

+2 −2
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	od_enc = ctl >> pll_info->od_shift;

	od_enc &= GENMASK(pll_info->od_bits - 1, 0);



	if (!pll_info->no_bypass_bit) {

	if (pll_info->bypass_bit >= 0) {

		ctl = readl(cgu->base + pll_info->bypass_reg);



		bypass = !!(ctl & BIT(pll_info->bypass_bit));
@@ -226,7 +226,7 @@ static int ingenic_pll_enable(struct clk_hw *hw) 
	u32 ctl;



	spin_lock_irqsave(&cgu->lock, flags);

	if (!pll_info->no_bypass_bit) {

	if (pll_info->bypass_bit >= 0) {

		ctl = readl(cgu->base + pll_info->bypass_reg);



		ctl &= ~BIT(pll_info->bypass_bit);

drivers/clk/ingenic/cgu.h

+3 −4
Original line number Diff line number Diff line
@@ -39,10 +39,10 @@ 
 *               their encoded values in the PLL control register, or -1 for

 *               unsupported values

 * @bypass_reg: the offset of the bypass control register within the CGU

 * @bypass_bit: the index of the bypass bit in the PLL control register

 * @bypass_bit: the index of the bypass bit in the PLL control register, or

 *              -1 if there is no bypass bit

 * @enable_bit: the index of the enable bit in the PLL control register

 * @stable_bit: the index of the stable bit in the PLL control register

 * @no_bypass_bit: if set, the PLL has no bypass functionality

 */

struct ingenic_cgu_pll_info {

	unsigned reg;
@@ -52,10 +52,9 @@ struct ingenic_cgu_pll_info { 
	u8 n_shift, n_bits, n_offset;

	u8 od_shift, od_bits, od_max;

	unsigned bypass_reg;

	u8 bypass_bit;

	s8 bypass_bit;

	u8 enable_bit;

	u8 stable_bit;

	bool no_bypass_bit;

};



/**

drivers/clk/ingenic/jz4770-cgu.c

+1 −2
Original line number Diff line number Diff line
@@ -139,8 +139,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { 
			.od_bits = 2,

			.od_max = 8,

			.od_encoding = pll_od_encoding,

			.bypass_reg = CGU_REG_CPPCR1,

			.no_bypass_bit = true,

			.bypass_bit = -1,

			.enable_bit = 7,

			.stable_bit = 6,

		},