Commit 0378ac5f authored by Shuai Wu's avatar Shuai Wu
Browse files

net/ethernet/huawei/hinic3: Add the CQM on which the RDMA depends 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9H643


CVE: NA

---------------------------------

Add Huawei Intelligent Network Card RDMA Driver Dependency.

Signed-off-by: default avatarShuai Wu <wushuai51@huawei.com>
parent a37954d8

Documentation/networking/hinic3.txt

+15 −0
Original line number Diff line number Diff line
@@ -81,6 +81,21 @@ Data. (hinic3_hw_qp.c, hinic3_hw_qp.h, hinic3_hw_qp_ctxt.h) 


IO - de/constructs all the IO components. (hinic3_hw_io.c, hinic3_hw_io.h)



CQM components:

==========



The CQM module organizes the memory in the large system in a format (CLA table)

and allocates the memory to the chip (BAT table). The chip can use the memory in

the large system to save context information and queue information (SCQ\SRQ).

(cqm_bat_cla.c, cqm_bat_cla.h, cqm_bitmap_table.c, cqm_bitmap_table.h)



When a packet is transmitted from the PCIe link, the chip parses the 5-tuple

such as sid, did, and hostid. Fill the parsed data in the queue

(in the form of scqe). In this way, the driver can directly obtain data from the

queue (through MPDK polling) and then process the data. In this way, the

uninstallation is implemented.

(cqm_main.c, cqm_main.h, cqm_db.c, cqm_db.h)



HW device:

==========

drivers/net/ethernet/huawei/hinic3/Makefile

+21 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/hw/

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/cqm/

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/cqm/

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/public/

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/cfg_mgmt/

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/mpu/

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/bond/

ccflags-y += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/vmsec/



obj-$(CONFIG_HINIC3) += hinic3.o

hinic3-objs := hw/hinic3_hwdev.o \
@@ -23,6 +32,8 @@ hinic3-objs := hw/hinic3_hwdev.o \ 
            hw/hinic3_nictool.o \

			hw/hinic3_devlink.o \

			hw/ossl_knl_linux.o \

			hw/hinic3_multi_host_mgmt.o \

			bond/hinic3_bond.o \

			hinic3_main.o \

			hinic3_tx.o \

			hinic3_rx.o \
@@ -42,4 +53,13 @@ hinic3-objs := hw/hinic3_hwdev.o \ 
			hinic3_rss_cfg.o \

			hinic3_nic_event.o \

			hinic3_nic_io.o \

			hinic3_nic_dbg.o
 
 No newline at end of file
 
			hinic3_nic_dbg.o \

			cqm/cqm_bat_cla.o \

			cqm/cqm_bitmap_table.o \

			cqm/cqm_object_intern.o \

			cqm/cqm_bloomfilter.o \

			cqm/cqm_cmd.o \

			cqm/cqm_db.o \

			cqm/cqm_object.o \

			cqm/cqm_main.o \

			cqm/cqm_memsec.o

drivers/net/ethernet/huawei/hinic3/bond/hinic3_bond.c

0 → 100644
+1042 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/huawei/hinic3/bond/hinic3_bond.h

0 → 100644
+98 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright(c) 2021 Huawei Technologies Co., Ltd */



#ifndef HINIC3_BOND_H

#define HINIC3_BOND_H



#include <linux/netdevice.h>

#include <linux/types.h>

#include "mpu_inband_cmd_defs.h"

#include "bond_common_defs.h"



enum hinic3_bond_user {

	HINIC3_BOND_USER_OVS,

	HINIC3_BOND_USER_TOE,

	HINIC3_BOND_USER_ROCE,

	HINIC3_BOND_USER_NUM

};



enum bond_service_proc_pos {

	BOND_BEFORE_ACTIVE,

	BOND_AFTER_ACTIVE,

	BOND_BEFORE_MODIFY,

	BOND_AFTER_MODIFY,

	BOND_BEFORE_DEACTIVE,

	BOND_AFTER_DEACTIVE,

	BOND_POS_MAX

};



#define BITMAP_SET(bm, bit)     ((bm) |= (typeof(bm))(1U << (bit)))

#define BITMAP_CLR(bm, bit)     ((bm) &= ~((typeof(bm))(1U << (bit))))

#define BITMAP_JUDGE(bm, bit)    ((bm) & (typeof(bm))(1U << (bit)))



#define MPU_CMD_BOND_CREATE     17

#define MPU_CMD_BOND_DELETE     18

#define MPU_CMD_BOND_SET_ATTR   19

#define MPU_CMD_BOND_GET_ATTR   20



#define HINIC3_MAX_PORT 4

#define HINIC3_IFNAMSIZ 16

struct hinic3_bond_info_s {

	u8 slaves;

	u8 cnt;

	u8 srv[2];

	char slaves_name[HINIC3_MAX_PORT][HINIC3_IFNAMSIZ];

};



#pragma pack(1)

struct netdev_lower_state_info {

	u8 link_up : 1;

	u8 tx_enabled : 1;

	u8 rsvd : 6;

};



#pragma pack()



struct bond_tracker {

	struct netdev_lower_state_info netdev_state[BOND_PORT_MAX_NUM];

	struct net_device *ndev[BOND_PORT_MAX_NUM];

	u8 cnt;

	bool is_bonded;

};



struct bond_attr {

	u16 bond_mode;

	u16 bond_id;

	u16 up_delay;

	u16 down_delay;

	u8 active_slaves;

	u8 slaves;

	u8 lacp_collect_slaves;

	u8 xmit_hash_policy;

	u32 first_roce_func;

	u32 bond_pf_bitmap;

	u32 user_bitmap;

};



struct hinic3_bond_cmd {

	u8 ret_status;

	u8 version;

	u16 sub_cmd;

	struct bond_attr attr;

	char bond_name[16];

};



void hinic3_bond_set_user_bitmap(struct bond_attr *attr, enum hinic3_bond_user user);

int hinic3_bond_attach(const char *name, enum hinic3_bond_user user, u16 *bond_id);

int hinic3_bond_detach(u16 bond_id, enum hinic3_bond_user user);

void hinic3_bond_clean_user(enum hinic3_bond_user user);

int hinic3_bond_get_uplink_id(u16 bond_id, u32 *uplink_id);

int hinic3_bond_register_service_func(enum hinic3_bond_user user, void (*func)

				      (const char *bond_name, void *bond_attr,

				      enum bond_service_proc_pos pos));

int hinic3_bond_unregister_service_func(enum hinic3_bond_user user);

int hinic3_bond_get_slaves(u16 bond_id, struct hinic3_bond_info_s *info);

struct net_device *hinic3_bond_get_netdev_by_portid(const char *bond_name, u8 port_id);

int hinic3_get_hw_bond_infos(void *hwdev, struct hinic3_hw_bond_infos *infos, u16 channel);

int hinic3_get_bond_tracker_by_name(const char *name, struct bond_tracker *tracker);

#endif /* HINIC3_BOND_H */

drivers/net/ethernet/huawei/hinic3/comm_msg_intf.h

+2 −563
Original line number Diff line number Diff line
@@ -14,69 +14,8 @@ 


#include "comm_defs.h"

#include "mgmt_msg_base.h"



/* func_reset_flag的边界值 */

#define FUNC_RESET_FLAG_MAX_VALUE ((1U << (RES_TYPE_MAX + 1)) - 1)

struct comm_cmd_func_reset {

	struct mgmt_msg_head head;



	u16 func_id;

	u16 rsvd1[3];

	u64 reset_flag;

};



struct comm_cmd_ppf_flr_type_set {

	struct mgmt_msg_head head;



	u16 func_id;

	u8 rsvd1[2];

	u32 ppf_flr_type;

};



enum {

	COMM_F_API_CHAIN = 1U << 0,

	COMM_F_CLP = 1U << 1,

	COMM_F_CHANNEL_DETECT = 1U << 2,

	COMM_F_MBOX_SEGMENT = 1U << 3,

	COMM_F_CMDQ_NUM = 1U << 4,

	COMM_F_VIRTIO_VQ_SIZE = 1U << 5,

};



#define COMM_MAX_FEATURE_QWORD 4

struct comm_cmd_feature_nego {

	struct mgmt_msg_head head;



	u16 func_id;

	u8 opcode; /* 1: set, 0: get */

	u8 rsvd;

	u64 s_feature[COMM_MAX_FEATURE_QWORD];

};



struct comm_cmd_clear_doorbell {

	struct mgmt_msg_head head;



	u16 func_id;

	u16 rsvd1[3];

};



struct comm_cmd_clear_resource {

	struct mgmt_msg_head head;



	u16 func_id;

	u16 rsvd1[3];

};



struct comm_global_attr {

	u8 max_host_num;

	u8 max_pf_num;

	u16 vf_id_start;



	u8 mgmt_host_node_id; /* for api cmd to mgmt cpu */

	u8 cmdq_num;

	u8 rsvd1[2];



	u32 rsvd2[8];

};

#include "mpu_cmd_base_defs.h"

#include "mpu_inband_cmd_defs.h"



struct spu_cmd_freq_operation {

	struct comm_info_head head;
@@ -107,236 +46,11 @@ struct spu_cmd_tsensor_operation { 
	s16 sys_tsensor_temp;

};



struct comm_cmd_heart_event {

	struct mgmt_msg_head head;



	u8 init_sta; /* 0: mpu init ok, 1: mpu init error. */

	u8 rsvd1[3];

	u32 heart;           /* add one by one */

	u32 heart_handshake; /* should be alwasys: 0x5A5A5A5A */

};



struct comm_cmd_channel_detect {

	struct mgmt_msg_head head;



	u16 func_id;

	u16 rsvd1[3];

	u32 rsvd2[2];

};



enum hinic3_svc_type {

	SVC_T_COMM = 0,

	SVC_T_NIC,

	SVC_T_OVS,

	SVC_T_ROCE,

	SVC_T_TOE,

	SVC_T_IOE,

	SVC_T_FC,

	SVC_T_VBS,

	SVC_T_IPSEC,

	SVC_T_VIRTIO,

	SVC_T_MIGRATE,

	SVC_T_PPA,

	SVC_T_MAX,

};



struct comm_cmd_func_svc_used_state {

	struct mgmt_msg_head head;

	u16 func_id;

	u16 svc_type;

	u8 used_state;

	u8 rsvd[35];

};



#define TABLE_INDEX_MAX 129



struct sml_table_id_info {

	u8 node_id;

	u8 instance_id;

};



struct comm_cmd_get_sml_tbl_data {

	struct comm_info_head head; /* 8B */

	u8 tbl_data[512];

};



struct comm_cmd_get_glb_attr {

	struct mgmt_msg_head head;



	struct comm_global_attr attr;

};



enum hinic3_fw_ver_type {

	HINIC3_FW_VER_TYPE_BOOT,

	HINIC3_FW_VER_TYPE_MPU,

	HINIC3_FW_VER_TYPE_NPU,

	HINIC3_FW_VER_TYPE_SMU_L0,

	HINIC3_FW_VER_TYPE_SMU_L1,

	HINIC3_FW_VER_TYPE_CFG,

};



#define HINIC3_FW_VERSION_LEN 16

#define HINIC3_FW_COMPILE_TIME_LEN 20

struct comm_cmd_get_fw_version {

	struct mgmt_msg_head head;



	u16 fw_type;

	u16 rsvd1;

	u8 ver[HINIC3_FW_VERSION_LEN];

	u8 time[HINIC3_FW_COMPILE_TIME_LEN];

};



/* hardware define: cmdq context */

struct cmdq_ctxt_info {

	u64 curr_wqe_page_pfn;

	u64 wq_block_pfn;

};



struct comm_cmd_cmdq_ctxt {

	struct mgmt_msg_head head;



	u16 func_id;

	u8 cmdq_id;

	u8 rsvd1[5];



	struct cmdq_ctxt_info ctxt;

};



struct comm_cmd_root_ctxt {

	struct mgmt_msg_head head;



	u16 func_id;

	u8 set_cmdq_depth;

	u8 cmdq_depth;

	u16 rx_buf_sz;

	u8 lro_en;

	u8 rsvd1;

	u16 sq_depth;

	u16 rq_depth;

	u64 rsvd2;

};



struct comm_cmd_wq_page_size {

	struct mgmt_msg_head head;



	u16 func_id;

	u8 opcode;

	/* real_size=4KB*2^page_size, range(0~20) must be checked by driver */

	u8 page_size;



	u32 rsvd1;

};



struct comm_cmd_msix_config {

	struct mgmt_msg_head head;



	u16 func_id;

	u8 opcode;

	u8 rsvd1;

	u16 msix_index;

	u8 pending_cnt;

	u8 coalesce_timer_cnt;

	u8 resend_timer_cnt;

	u8 lli_timer_cnt;

	u8 lli_credit_cnt;

	u8 rsvd2[5];

};



enum cfg_msix_operation {

	CFG_MSIX_OPERATION_FREE = 0,

	CFG_MSIX_OPERATION_ALLOC = 1,

};



struct comm_cmd_cfg_msix_num {

	struct comm_info_head head; /* 8B */



	u16 func_id;

	u8 op_code; /* 1: alloc 0: free */

	u8 rsvd0;



	u16 msix_num;

	u16 rsvd1;

};



struct comm_cmd_dma_attr_config {

	struct mgmt_msg_head head;



	u16 func_id;

	u8 entry_idx;

	u8 st;

	u8 at;

	u8 ph;

	u8 no_snooping;

	u8 tph_en;

	u32 resv1;

};



struct comm_cmd_ceq_ctrl_reg {

	struct mgmt_msg_head head;



	u16 func_id;

	u16 q_id;

	u32 ctrl0;

	u32 ctrl1;

	u32 rsvd1;

};



struct comm_cmd_func_tmr_bitmap_op {

	struct mgmt_msg_head head;



	u16 func_id;

	u8 opcode; /* 1: start, 0: stop */

	u8 rsvd1[5];

};



struct comm_cmd_ppf_tmr_op {

	struct mgmt_msg_head head;



	u8 ppf_id;

	u8 opcode; /* 1: start, 0: stop */

	u8 rsvd1[6];

};



struct comm_cmd_ht_gpa {

	struct mgmt_msg_head head;



	u8 host_id;

	u8 rsvd0[3];

	u32 rsvd1[7];

	u64 page_pa0;

	u64 page_pa1;

};



struct comm_cmd_get_eqm_num {

	struct mgmt_msg_head head;



	u8 host_id;

	u8 rsvd1[3];

	u32 chunk_num;

	u32 search_gpa_num;

};



struct comm_cmd_eqm_cfg {

	struct mgmt_msg_head head;



	u8 host_id;

	u8 valid;

	u16 rsvd1;

	u32 page_size;

	u32 rsvd2;

};



struct comm_cmd_eqm_search_gpa {

	struct mgmt_msg_head head;



	u8 host_id;

	u8 rsvd1[3];

	u32 start_idx;

	u32 num;

	u32 rsvd2;

	u64 gpa_hi52[0]; /*lint !e1501*/

};



struct comm_cmd_ffm_info {

	struct mgmt_msg_head head;
@@ -350,281 +64,6 @@ struct comm_cmd_ffm_info { 
	u32 rsvd1;

};



#define HARDWARE_ID_1XX3V100_TAG 31 /* 1xx3v100 tag */



struct hinic3_board_info {

	u8 board_type;

	u8 port_num;

	u8 port_speed;

	u8 pcie_width;

	u8 host_num;

	u8 pf_num;

	u16 vf_total_num;

	u8 tile_num;

	u8 qcm_num;

	u8 core_num;

	u8 work_mode;

	u8 service_mode;

	u8 pcie_mode;

	u8 boot_sel;

	u8 board_id;

	u32 cfg_addr;

	u32 service_en_bitmap;

	u8 scenes_id;

	u8 cfg_template_id;

	u8 hardware_id;

	u8 spu_en;

	u16 pf_vendor_id;

	u8 tile_bitmap;

	u8 sm_bitmap;

};



struct comm_cmd_board_info {

	struct mgmt_msg_head head;



	struct hinic3_board_info info;

	u32 rsvd[22];

};



struct comm_cmd_sync_time {

	struct mgmt_msg_head head;



	u64 mstime;

	u64 rsvd1;

};



struct comm_cmd_sdi_info {

	struct mgmt_msg_head head;

	u32 cfg_sdi_mode;

};



/* func flr set */

struct comm_cmd_func_flr_set {

	struct mgmt_msg_head head;



	u16 func_id;

	u8 type;  /* 1: close 置flush */

	u8 isall; /* 是否操作对应pf下的所有vf 1: all vf */

	u32 rsvd;

};



struct comm_cmd_bdf_info {

	struct mgmt_msg_head head;



	u16 function_idx;

	u8 rsvd1[2];

	u8 bus;

	u8 device;

	u8 function;

	u8 rsvd2[5];

};



struct hw_pf_info {

	u16 glb_func_idx;

	u16 glb_pf_vf_offset;

	u8 p2p_idx;

	u8 itf_idx;

	u16 max_vfs;

	u16 max_queue_num;

	u16 vf_max_queue_num;

	u16 port_id;

	u16 rsvd0;

	u32 pf_service_en_bitmap;

	u32 vf_service_en_bitmap;

	u16 rsvd1[2];



	u8 device_type;

	u8 bus_num;    /* tl_cfg_bus_num */

	u16 vf_stride; /* VF_RID_SETTING.vf_stride */

	u16 vf_offset; /* VF_RID_SETTING.vf_offset */

	u8 rsvd[2];

};



#define CMD_MAX_MAX_PF_NUM 32

struct hinic3_hw_pf_infos {

	u8 num_pfs;

	u8 rsvd1[3];



	struct hw_pf_info infos[CMD_MAX_MAX_PF_NUM];

};



struct comm_cmd_hw_pf_infos {

	struct mgmt_msg_head head;



	struct hinic3_hw_pf_infos infos;

};



#define DD_CFG_TEMPLATE_MAX_IDX 12

#define DD_CFG_TEMPLATE_MAX_TXT_LEN 64

#define CFG_TEMPLATE_OP_QUERY 0

#define CFG_TEMPLATE_OP_SET 1

#define CFG_TEMPLATE_SET_MODE_BY_IDX 0

#define CFG_TEMPLATE_SET_MODE_BY_NAME 1



struct comm_cmd_cfg_template {

	struct mgmt_msg_head head;

	u8 opt_type; /* 0: query  1: set */

	u8 set_mode; /* 0-index mode. 1-name mode. */

	u8 tp_err;

	u8 rsvd0;



	u8 cur_index;     /* Current cfg tempalte index. */

	u8 cur_max_index; /* Max support cfg tempalte index. */

	u8 rsvd1[2];

	u8 cur_name[DD_CFG_TEMPLATE_MAX_TXT_LEN];

	u8 cur_cfg_temp_info[DD_CFG_TEMPLATE_MAX_IDX][DD_CFG_TEMPLATE_MAX_TXT_LEN];



	u8 next_index;     /* Next reset cfg tempalte index. */

	u8 next_max_index; /* Max support cfg tempalte index. */

	u8 rsvd2[2];

	u8 next_name[DD_CFG_TEMPLATE_MAX_TXT_LEN];

	u8 next_cfg_temp_info[DD_CFG_TEMPLATE_MAX_IDX][DD_CFG_TEMPLATE_MAX_TXT_LEN];

};



#define MQM_SUPPORT_COS_NUM 8

#define MQM_INVALID_WEIGHT 256

#define MQM_LIMIT_SET_FLAG_READ 0

#define MQM_LIMIT_SET_FLAG_WRITE 1

struct comm_cmd_set_mqm_limit {

	struct mgmt_msg_head head;



	u16 set_flag; /* 置位该标记位表示设置 */

	u16 func_id;

	/* 对应cos_id所占的权重，0-255, 0为SP调度. */

	u16 cos_weight[MQM_SUPPORT_COS_NUM];

	u32 host_min_rate; /* 本host支持的最低限速 */

	u32 func_min_rate; /* 本function支持的最低限速，单位Mbps */

	u32 func_max_rate; /* 本function支持的最高限速，单位Mbps  */

	u8 rsvd[64]; /* Reserved */

};



#define DUMP_16B_PER_LINE	16

#define DUMP_8_VAR_PER_LINE	8

#define DUMP_4_VAR_PER_LINE	4



#define DATA_LEN_1K 1024

/* 软狗超时信息上报接口 */

struct comm_info_sw_watchdog {

	struct comm_info_head head;



	/* 全局信息 */

	u32 curr_time_h; /* 发生死循环的时间,cycle */

	u32 curr_time_l; /* 发生死循环的时间,cycle */

	u32 task_id;     /* 发生死循环的任务       */

	u32 rsv;         /* 保留字段，用于扩展     */



	/* 寄存器信息，TSK_CONTEXT_S */

	u64 pc;



	u64 elr;

	u64 spsr;

	u64 far;

	u64 esr;

	u64 xzr;

	u64 x30;

	u64 x29;

	u64 x28;

	u64 x27;

	u64 x26;

	u64 x25;

	u64 x24;

	u64 x23;

	u64 x22;

	u64 x21;

	u64 x20;

	u64 x19;

	u64 x18;

	u64 x17;

	u64 x16;

	u64 x15;

	u64 x14;

	u64 x13;

	u64 x12;

	u64 x11;

	u64 x10;

	u64 x09;

	u64 x08;

	u64 x07;

	u64 x06;

	u64 x05;

	u64 x04;

	u64 x03;

	u64 x02;

	u64 x01;

	u64 x00;



	/* 堆栈控制信息，STACK_INFO_S */

	u64 stack_top;    /* 栈顶                   */

	u64 stack_bottom; /* 栈底                   */

	u64 sp;           /* 栈当前SP指针值         */

	u32 curr_used;          /* 栈当前使用的大小       */

	u32 peak_used;          /* 栈使用的历史峰值       */

	u32 is_overflow;        /* 栈是否溢出             */



	/* 堆栈具体内容 */

	u32 stack_actlen;      /* 实际的堆栈长度(<=1024) */

	u8 stack_data[DATA_LEN_1K]; /* 超过1024部分，会被截断 */

};



/* 临终遗言信息 */

#define XREGS_NUM 31

struct tag_cpu_tick {

	u32 cnt_hi; /* *<  cycle计数高32位 */

	u32 cnt_lo; /* *<  cycle计数低32位 */

};



struct tag_ax_exc_reg_info {

	u64 ttbr0;

	u64 ttbr1;

	u64 tcr;

	u64 mair;

	u64 sctlr;

	u64 vbar;

	u64 current_el;

	u64 sp;

	/* 以下字段的内存布局与TskContext保持一致 */

	u64 elr;               /* 返回地址 */

	u64 spsr;

	u64 far_r;

	u64 esr;

	u64 xzr;

	u64 xregs[XREGS_NUM];         /* 0~30: x30~x0 */

};



struct tag_exc_info {

	char os_ver[48];   /* *< OS版本号 */

	char app_ver[64];  /* *< 产品版本号 */

	u32 exc_cause;     /* *< 异常原因 */

	u32 thread_type;   /* *< 异常前的线程类型 */

	u32 thread_id;     /* *< 异常前线程PID */

	u16 byte_order;    /* *< 字节序 */

	u16 cpu_type;      /* *< CPU类型 */

	u32 cpu_id;        /* *< CPU ID */

	struct tag_cpu_tick cpu_tick; /* *< CPU Tick */

	u32 nest_cnt;      /* *< 异常嵌套计数 */

	u32 fatal_errno;     /* *< 致命错误码，发生致命错误时有效 */

	u64 uw_sp;           /* *< 异常前栈指针 */

	u64 stack_bottom;  /* *< 异常前栈底 */

	/* 异常发生时的核内寄存器上下文信息，82\57必须位于152字节处，

	 * 若有改动，需更新sre_platform.eh中的OS_EXC_REGINFO_OFFSET宏

	 */

	struct tag_ax_exc_reg_info reg_info;

};



/* 上报给驱动的up lastword模块接口 */

#define MPU_LASTWORD_SIZE 1024

struct tag_comm_info_up_lastword {

	struct comm_info_head head;



	struct tag_exc_info stack_info;



	/* 堆栈具体内容 */

	u32 stack_actlen; /* 实际的堆栈长度(<=1024) */

	u8 stack_data[MPU_LASTWORD_SIZE]; /* 超过1024部分，会被截断 */

};



#define FW_UPDATE_MGMT_TIMEOUT	3000000U



struct hinic3_cmd_update_firmware {

	struct mgmt_msg_head msg_head;