Commit 0376f6ec authored by Leonard Crestez's avatar Leonard Crestez Committed by Shawn Guo
Browse files

arm64: dts: imx8m: Add ddr controller nodes 



This is used by the imx-ddrc devfreq driver to implement dynamic
frequency scaling of DRAM.

Support for proactive scaling via interconnect will come later. The
high-performance bus masters which need that (display, vpu, gpu) are
mostly not yet enabled in upstream anyway.

Signed-off-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0f93eb28

arch/arm64/boot/dts/freescale/imx8mm-evk.dts

+20 −0
Original line number Diff line number Diff line
@@ -77,6 +77,26 @@ 
	cpu-supply = <&buck2_reg>;

};



&ddrc {

	operating-points-v2 = <&ddrc_opp_table>;



	ddrc_opp_table: opp-table {

		compatible = "operating-points-v2";



		opp-25M {

			opp-hz = /bits/ 64 <25000000>;

		};



		opp-100M {

			opp-hz = /bits/ 64 <100000000>;

		};



		opp-750M {

			opp-hz = /bits/ 64 <750000000>;

		};

	};

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_fec1>;

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -858,6 +858,16 @@ 
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		ddrc: memory-controller@3d400000 {

			compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";

			reg = <0x3d400000 0x400000>;

			clock-names = "core", "pll", "alt", "apb";

			clocks = <&clk IMX8MM_CLK_DRAM_CORE>,

				 <&clk IMX8MM_DRAM_PLL>,

				 <&clk IMX8MM_CLK_DRAM_ALT>,

				 <&clk IMX8MM_CLK_DRAM_APB>;

		};



		ddr-pmu@3d800000 {

			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";

			reg = <0x3d800000 0x400000>;

arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts

+20 −0
Original line number Diff line number Diff line
@@ -17,6 +17,26 @@ 
	cpu-supply = <&buck2_reg>;

};



&ddrc {

	operating-points-v2 = <&ddrc_opp_table>;



	ddrc_opp_table: opp-table {

		compatible = "operating-points-v2";



		opp-25M {

			opp-hz = /bits/ 64 <25000000>;

		};



		opp-100M {

			opp-hz = /bits/ 64 <100000000>;

		};



		opp-600M {

			opp-hz = /bits/ 64 <600000000>;

		};

	};

};



&i2c1 {

	pmic@4b {

		compatible = "rohm,bd71847";

arch/arm64/boot/dts/freescale/imx8mn.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -759,6 +759,16 @@ 
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		ddrc: memory-controller@3d400000 {

			compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";

			reg = <0x3d400000 0x400000>;

			clock-names = "core", "pll", "alt", "apb";

			clocks = <&clk IMX8MN_CLK_DRAM_CORE>,

				 <&clk IMX8MN_DRAM_PLL>,

				 <&clk IMX8MN_CLK_DRAM_ALT>,

				 <&clk IMX8MN_CLK_DRAM_APB>;

		};



		ddr-pmu@3d800000 {

			compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";

			reg = <0x3d800000 0x400000>;

arch/arm64/boot/dts/freescale/imx8mq-evk.dts

+27 −0
Original line number Diff line number Diff line
@@ -105,6 +105,33 @@ 
	cpu-supply = <&buck2_reg>;

};



&ddrc {

	operating-points-v2 = <&ddrc_opp_table>;



	ddrc_opp_table: opp-table {

		compatible = "operating-points-v2";



		opp-25M {

			opp-hz = /bits/ 64 <25000000>;

		};



		opp-100M {

			opp-hz = /bits/ 64 <100000000>;

		};



		/*

		 * On imx8mq B0 PLL can't be bypassed so low bus is 166M

		 */

		opp-166M {

			opp-hz = /bits/ 64 <166935483>;

		};



		opp-800M {

			opp-hz = /bits/ 64 <800000000>;

		};

	};

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_fec1>;