Commit 0349af70 authored Mar 14, 2012 by Michel Dänzer Committed by Dave Airlie Mar 20, 2012

drm/radeon: Restrict offset for legacy display engine.



The hardware only takes 27 bits for the offset, so larger offsets are
truncated, and the display shows random bits other than the intended ones.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

parent c4353016

drivers/gpu/drm/radeon/radeon_display.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -402,7 +402,9 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
		DRM_ERROR("failed to reserve new rbo buffer before flip\n");
		goto pflip_cleanup;
		}
		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
		/* Only 27 bit offset for legacy CRTC */
		r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
		ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
		if (unlikely(r != 0)) {
		radeon_bo_unreserve(rbo);
		r = -EINVAL;

drivers/gpu/drm/radeon/radeon_fb.c

+4 −1

Original line number	Diff line number	Diff line
		@@ -164,7 +164,10 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
		ret = radeon_bo_reserve(rbo, false);
		if (unlikely(ret != 0))
		goto out_unref;
		ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
		/* Only 27 bit offset for legacy CRTC */
		ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
		ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
		NULL);
		if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -419,7 +419,9 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
		r = radeon_bo_reserve(rbo, false);
		if (unlikely(r != 0))
		return r;
		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
		/* Only 27 bit offset for legacy CRTC */
		r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
		&base);
		if (unlikely(r != 0)) {
		radeon_bo_unreserve(rbo);
		return -EINVAL;