Commit 02ff519e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: make mcbp a per device setting 



So we can selectively enable it on certain devices.  No
intended functional change.

Reviewed-and-tested-by: default avatarJiadong Zhu <Jiadong.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5efe0f3e

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+15 −4
Original line number Diff line number Diff line
@@ -2552,7 +2552,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) 
			adev->ip_blocks[i].status.hw = true;



			/* right after GMC hw init, we create CSA */

			if (amdgpu_mcbp) {

			if (adev->gfx.mcbp) {

				r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,

							       AMDGPU_GEM_DOMAIN_VRAM |

							       AMDGPU_GEM_DOMAIN_GTT,
@@ -3673,6 +3673,18 @@ static const struct attribute *amdgpu_dev_attributes[] = { 
	NULL

};



static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)

{

	if (amdgpu_mcbp == 1)

		adev->gfx.mcbp = true;



	if (amdgpu_sriov_vf(adev))

		adev->gfx.mcbp = true;



	if (adev->gfx.mcbp)

		DRM_INFO("MCBP is enabled\n");

}



/**

 * amdgpu_device_init - initialize the driver

 *
@@ -3824,9 +3836,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);

	DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);



	if (amdgpu_mcbp)

		DRM_INFO("MCBP is enabled\n");



	/*

	 * Reset domain needs to be present early, before XGMI hive discovered

	 * (if any) and intitialized to use reset sem and in_gpu reset flag
@@ -3852,6 +3861,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	if (r)

		return r;



	amdgpu_device_set_mcbp(adev);



	/* Get rid of things like offb */

	r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);

	if (r)

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+1 −0
Original line number Diff line number Diff line
@@ -434,6 +434,7 @@ struct amdgpu_gfx { 
	uint16_t 			xcc_mask;

	uint32_t			num_xcc_per_xcp;

	struct mutex			partition_mutex;

	bool				mcbp; /* mid command buffer preemption */

};



struct amdgpu_gfx_ras_reg_entry {

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+2 −2
Original line number Diff line number Diff line
@@ -805,7 +805,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
		dev_info->ids_flags = 0;

		if (adev->flags & AMD_IS_APU)

			dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;

		if (amdgpu_mcbp)

		if (adev->gfx.mcbp)

			dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;

		if (amdgpu_is_tmz(adev))

			dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
@@ -1247,7 +1247,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 
		goto error_vm;

	}



	if (amdgpu_mcbp) {

	if (adev->gfx.mcbp) {

		uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;



		r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,

drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c

+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, 
	int r;



	/* don't enable OS preemption on SDMA under SRIOV */

	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)

	if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp)

		return 0;



	if (ring->is_mes_queue) {

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+0 −3
Original line number Diff line number Diff line
@@ -66,9 +66,6 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) 
	adev->cg_flags = 0;

	adev->pg_flags = 0;



	/* enable mcbp for sriov */

	amdgpu_mcbp = 1;



	/* Reduce kcq number to 2 to reduce latency */

	if (amdgpu_num_kcq == -1)

		amdgpu_num_kcq = 2;