Commit 02f958a2 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: refactor function to init no-psp fw 



Refactor the code of amdgpu_ucode_init_single_fw to make it more
readable as too many ucode need to handle on this function currently.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 06dd1888

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

+75 −85
Original line number Diff line number Diff line
@@ -572,6 +572,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 
	const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;

	const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;

	const struct mes_firmware_header_v1_0 *mes_hdr = NULL;

	u8 *ucode_addr;



	if (NULL == ucode->fw)

		return 0;
@@ -588,94 +589,83 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 
	dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;

	mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;



	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||

	    (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM &&

		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&

		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&

		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {

		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);



		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +

					      le32_to_cpu(header->ucode_array_offset_bytes)),

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||

		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {

	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		switch (ucode->ucode_id) {

		case AMDGPU_UCODE_ID_CP_MEC1:

		case AMDGPU_UCODE_ID_CP_MEC2:

			ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -

				le32_to_cpu(cp_hdr->jt_size) * 4;



		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +

					      le32_to_cpu(header->ucode_array_offset_bytes)),

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||

		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(header->ucode_array_offset_bytes);

			break;

		case AMDGPU_UCODE_ID_CP_MEC1_JT:

		case AMDGPU_UCODE_ID_CP_MEC2_JT:

			ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;



		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(header->ucode_array_offset_bytes) +

					      le32_to_cpu(cp_hdr->jt_offset) * 4),

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {

		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -

				le32_to_cpu(dmcu_hdr->intv_size_bytes);



		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +

					      le32_to_cpu(header->ucode_array_offset_bytes)),

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {

		ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);



		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +

					      le32_to_cpu(header->ucode_array_offset_bytes) +

					      le32_to_cpu(dmcu_hdr->intv_offset_bytes)),

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) {

		ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);

		memcpy(ucode->kaddr,

		       (void *)((uint8_t *)ucode->fw->data +

				le32_to_cpu(header->ucode_array_offset_bytes)),

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {

				le32_to_cpu(cp_hdr->jt_offset) * 4;

			break;

		case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:

			ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {

			ucode_addr = adev->gfx.rlc.save_restore_list_cntl;

			break;

		case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:

			ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {

			ucode_addr = adev->gfx.rlc.save_restore_list_gpm;

			break;

		case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:

			ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) {

			ucode_addr = adev->gfx.rlc.save_restore_list_srm;

			break;

		case AMDGPU_UCODE_ID_RLC_IRAM:

			ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) {

			ucode_addr = adev->gfx.rlc.rlc_iram_ucode;

			break;

		case AMDGPU_UCODE_ID_RLC_DRAM:

			ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {

			ucode_addr = adev->gfx.rlc.rlc_dram_ucode;

			break;

		case AMDGPU_UCODE_ID_CP_MES:

			ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);

		memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +

			      le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)),

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) {

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);

			break;

		case AMDGPU_UCODE_ID_CP_MES_DATA:

			ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);

		memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +

			      le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)),

		       ucode->ucode_size);

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);

			break;

		case AMDGPU_UCODE_ID_DMCU_ERAM:

			ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -

				le32_to_cpu(dmcu_hdr->intv_size_bytes);

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(header->ucode_array_offset_bytes);

			break;

		case AMDGPU_UCODE_ID_DMCU_INTV:

			ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(header->ucode_array_offset_bytes) +

				le32_to_cpu(dmcu_hdr->intv_offset_bytes);

			break;

		case AMDGPU_UCODE_ID_DMCUB:

			ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(header->ucode_array_offset_bytes);

			break;

		default:

			ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);

			ucode_addr = (u8 *)ucode->fw->data +

				le32_to_cpu(header->ucode_array_offset_bytes);

			break;

		}

	} else {

		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);

		ucode_addr = (u8 *)ucode->fw->data +

			le32_to_cpu(header->ucode_array_offset_bytes);

	}



	memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);



	return 0;

}