Commit 02f6fdd4 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch kvm-arm64/selftest/linked-bps into kvmarm-master/next 



* kvm-arm64/selftest/linked-bps:
  : .
  : Additional selftests for the arm64 breakpoints/watchpoints,
  : courtesy of Reiji Watanabe. From the cover letter:
  :
  : "This series adds test cases for linked {break,watch}points to the
  : debug-exceptions test, and expands {break,watch}point tests to
  : use non-zero {break,watch}points (the current test always uses
  : {break,watch}point#0)."
  : .
  KVM: arm64: selftests: Test with every breakpoint/watchpoint
  KVM: arm64: selftests: Add a test case for a linked watchpoint
  KVM: arm64: selftests: Add a test case for a linked breakpoint
  KVM: arm64: selftests: Change debug_version() to take ID_AA64DFR0_EL1
  KVM: arm64: selftests: Stop unnecessary test stage tracking of debug-exceptions
  KVM: arm64: selftests: Add helpers to enable debug exceptions
  KVM: arm64: selftests: Remove the hard-coded {b,w}pn#0 from debug-exceptions
  KVM: arm64: selftests: Add write_dbg{b,w}{c,v}r helpers in debug-exceptions
  KVM: arm64: selftests: Use FIELD_GET() to extract ID register fields

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents f8faf02f ebb8cc10

tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c

+2 −1
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include "kvm_util.h"

#include "processor.h"

#include "test_util.h"

#include <linux/bitfield.h>



#define BAD_ID_REG_VAL	0x1badc0deul
@@ -145,7 +146,7 @@ static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu) 


	vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);



	el0 = (val & ARM64_FEATURE_MASK(ID_AA64PFR0_EL0)) >> ID_AA64PFR0_EL0_SHIFT;

	el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL0), val);

	return el0 == ID_AA64PFR0_ELx_64BIT_ONLY;

}

tools/testing/selftests/kvm/aarch64/debug-exceptions.c

+239 −72
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#include <test_util.h>

#include <kvm_util.h>

#include <processor.h>

#include <linux/bitfield.h>



#define MDSCR_KDE	(1 << 13)

#define MDSCR_MDE	(1 << 15)
@@ -11,17 +12,24 @@ 
#define DBGBCR_EXEC	(0x0 << 3)

#define DBGBCR_EL1	(0x1 << 1)

#define DBGBCR_E	(0x1 << 0)

#define DBGBCR_LBN_SHIFT	16

#define DBGBCR_BT_SHIFT		20

#define DBGBCR_BT_ADDR_LINK_CTX	(0x1 << DBGBCR_BT_SHIFT)

#define DBGBCR_BT_CTX_LINK	(0x3 << DBGBCR_BT_SHIFT)



#define DBGWCR_LEN8	(0xff << 5)

#define DBGWCR_RD	(0x1 << 3)

#define DBGWCR_WR	(0x2 << 3)

#define DBGWCR_EL1	(0x1 << 1)

#define DBGWCR_E	(0x1 << 0)

#define DBGWCR_LBN_SHIFT	16

#define DBGWCR_WT_SHIFT		20

#define DBGWCR_WT_LINK		(0x1 << DBGWCR_WT_SHIFT)



#define SPSR_D		(1 << 9)

#define SPSR_SS		(1 << 21)



extern unsigned char sw_bp, sw_bp2, hw_bp, hw_bp2, bp_svc, bp_brk, hw_wp, ss_start;

extern unsigned char sw_bp, sw_bp2, hw_bp, hw_bp2, bp_svc, bp_brk, hw_wp, ss_start, hw_bp_ctx;

extern unsigned char iter_ss_begin, iter_ss_end;

static volatile uint64_t sw_bp_addr, hw_bp_addr;

static volatile uint64_t wp_addr, wp_data_addr;
@@ -29,8 +37,74 @@ static volatile uint64_t svc_addr; 
static volatile uint64_t ss_addr[4], ss_idx;

#define  PC(v)  ((uint64_t)&(v))



#define GEN_DEBUG_WRITE_REG(reg_name)			\

static void write_##reg_name(int num, uint64_t val)	\

{							\

	switch (num) {					\

	case 0:						\

		write_sysreg(val, reg_name##0_el1);	\

		break;					\

	case 1:						\

		write_sysreg(val, reg_name##1_el1);	\

		break;					\

	case 2:						\

		write_sysreg(val, reg_name##2_el1);	\

		break;					\

	case 3:						\

		write_sysreg(val, reg_name##3_el1);	\

		break;					\

	case 4:						\

		write_sysreg(val, reg_name##4_el1);	\

		break;					\

	case 5:						\

		write_sysreg(val, reg_name##5_el1);	\

		break;					\

	case 6:						\

		write_sysreg(val, reg_name##6_el1);	\

		break;					\

	case 7:						\

		write_sysreg(val, reg_name##7_el1);	\

		break;					\

	case 8:						\

		write_sysreg(val, reg_name##8_el1);	\

		break;					\

	case 9:						\

		write_sysreg(val, reg_name##9_el1);	\

		break;					\

	case 10:					\

		write_sysreg(val, reg_name##10_el1);	\

		break;					\

	case 11:					\

		write_sysreg(val, reg_name##11_el1);	\

		break;					\

	case 12:					\

		write_sysreg(val, reg_name##12_el1);	\

		break;					\

	case 13:					\

		write_sysreg(val, reg_name##13_el1);	\

		break;					\

	case 14:					\

		write_sysreg(val, reg_name##14_el1);	\

		break;					\

	case 15:					\

		write_sysreg(val, reg_name##15_el1);	\

		break;					\

	default:					\

		GUEST_ASSERT(0);			\

	}						\

}



/* Define write_dbgbcr()/write_dbgbvr()/write_dbgwcr()/write_dbgwvr() */

GEN_DEBUG_WRITE_REG(dbgbcr)

GEN_DEBUG_WRITE_REG(dbgbvr)

GEN_DEBUG_WRITE_REG(dbgwcr)

GEN_DEBUG_WRITE_REG(dbgwvr)



static void reset_debug_state(void)

{

	uint8_t brps, wrps, i;

	uint64_t dfr0;



	asm volatile("msr daifset, #8");



	write_sysreg(0, osdlr_el1);
@@ -38,11 +112,21 @@ static void reset_debug_state(void) 
	isb();



	write_sysreg(0, mdscr_el1);

	/* This test only uses the first bp and wp slot. */

	write_sysreg(0, dbgbvr0_el1);

	write_sysreg(0, dbgbcr0_el1);

	write_sysreg(0, dbgwcr0_el1);

	write_sysreg(0, dbgwvr0_el1);

	write_sysreg(0, contextidr_el1);



	/* Reset all bcr/bvr/wcr/wvr registers */

	dfr0 = read_sysreg(id_aa64dfr0_el1);

	brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS), dfr0);

	for (i = 0; i <= brps; i++) {

		write_dbgbcr(i, 0);

		write_dbgbvr(i, 0);

	}

	wrps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS), dfr0);

	for (i = 0; i <= wrps; i++) {

		write_dbgwcr(i, 0);

		write_dbgwvr(i, 0);

	}



	isb();

}
@@ -54,16 +138,10 @@ static void enable_os_lock(void) 
	GUEST_ASSERT(read_sysreg(oslsr_el1) & 2);

}



static void install_wp(uint64_t addr)

static void enable_monitor_debug_exceptions(void)

{

	uint32_t wcr;

	uint32_t mdscr;



	wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E;

	write_sysreg(wcr, dbgwcr0_el1);

	write_sysreg(addr, dbgwvr0_el1);

	isb();



	asm volatile("msr daifclr, #8");



	mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_MDE;
@@ -71,21 +149,76 @@ static void install_wp(uint64_t addr) 
	isb();

}



static void install_hw_bp(uint64_t addr)

static void install_wp(uint8_t wpn, uint64_t addr)

{

	uint32_t wcr;



	wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E;

	write_dbgwcr(wpn, wcr);

	write_dbgwvr(wpn, addr);



	isb();



	enable_monitor_debug_exceptions();

}



static void install_hw_bp(uint8_t bpn, uint64_t addr)

{

	uint32_t bcr;

	uint32_t mdscr;



	bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E;

	write_sysreg(bcr, dbgbcr0_el1);

	write_sysreg(addr, dbgbvr0_el1);

	write_dbgbcr(bpn, bcr);

	write_dbgbvr(bpn, addr);

	isb();



	asm volatile("msr daifclr, #8");

	enable_monitor_debug_exceptions();

}



	mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_MDE;

	write_sysreg(mdscr, mdscr_el1);

static void install_wp_ctx(uint8_t addr_wp, uint8_t ctx_bp, uint64_t addr,

			   uint64_t ctx)

{

	uint32_t wcr;

	uint64_t ctx_bcr;



	/* Setup a context-aware breakpoint for Linked Context ID Match */

	ctx_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E |

		  DBGBCR_BT_CTX_LINK;

	write_dbgbcr(ctx_bp, ctx_bcr);

	write_dbgbvr(ctx_bp, ctx);



	/* Setup a linked watchpoint (linked to the context-aware breakpoint) */

	wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E |

	      DBGWCR_WT_LINK | ((uint32_t)ctx_bp << DBGWCR_LBN_SHIFT);

	write_dbgwcr(addr_wp, wcr);

	write_dbgwvr(addr_wp, addr);

	isb();



	enable_monitor_debug_exceptions();

}



void install_hw_bp_ctx(uint8_t addr_bp, uint8_t ctx_bp, uint64_t addr,

		       uint64_t ctx)

{

	uint32_t addr_bcr, ctx_bcr;



	/* Setup a context-aware breakpoint for Linked Context ID Match */

	ctx_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E |

		  DBGBCR_BT_CTX_LINK;

	write_dbgbcr(ctx_bp, ctx_bcr);

	write_dbgbvr(ctx_bp, ctx);



	/*

	 * Setup a normal breakpoint for Linked Address Match, and link it

	 * to the context-aware breakpoint.

	 */

	addr_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E |

		   DBGBCR_BT_ADDR_LINK_CTX |

		   ((uint32_t)ctx_bp << DBGBCR_LBN_SHIFT);

	write_dbgbcr(addr_bp, addr_bcr);

	write_dbgbvr(addr_bp, addr);

	isb();



	enable_monitor_debug_exceptions();

}



static void install_ss(void)
@@ -101,52 +234,42 @@ static void install_ss(void) 


static volatile char write_data;



static void guest_code(void)

static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn)

{

	GUEST_SYNC(0);

	uint64_t ctx = 0xabcdef;	/* a random context number */



	/* Software-breakpoint */

	reset_debug_state();

	asm volatile("sw_bp: brk #0");

	GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp));



	GUEST_SYNC(1);



	/* Hardware-breakpoint */

	reset_debug_state();

	install_hw_bp(PC(hw_bp));

	install_hw_bp(bpn, PC(hw_bp));

	asm volatile("hw_bp: nop");

	GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp));



	GUEST_SYNC(2);



	/* Hardware-breakpoint + svc */

	reset_debug_state();

	install_hw_bp(PC(bp_svc));

	install_hw_bp(bpn, PC(bp_svc));

	asm volatile("bp_svc: svc #0");

	GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_svc));

	GUEST_ASSERT_EQ(svc_addr, PC(bp_svc) + 4);



	GUEST_SYNC(3);



	/* Hardware-breakpoint + software-breakpoint */

	reset_debug_state();

	install_hw_bp(PC(bp_brk));

	install_hw_bp(bpn, PC(bp_brk));

	asm volatile("bp_brk: brk #0");

	GUEST_ASSERT_EQ(sw_bp_addr, PC(bp_brk));

	GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_brk));



	GUEST_SYNC(4);



	/* Watchpoint */

	reset_debug_state();

	install_wp(PC(write_data));

	install_wp(wpn, PC(write_data));

	write_data = 'x';

	GUEST_ASSERT_EQ(write_data, 'x');

	GUEST_ASSERT_EQ(wp_data_addr, PC(write_data));



	GUEST_SYNC(5);



	/* Single-step */

	reset_debug_state();

	install_ss();
@@ -160,8 +283,6 @@ static void guest_code(void) 
	GUEST_ASSERT_EQ(ss_addr[1], PC(ss_start) + 4);

	GUEST_ASSERT_EQ(ss_addr[2], PC(ss_start) + 8);



	GUEST_SYNC(6);



	/* OS Lock does not block software-breakpoint */

	reset_debug_state();

	enable_os_lock();
@@ -169,30 +290,24 @@ static void guest_code(void) 
	asm volatile("sw_bp2: brk #0");

	GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp2));



	GUEST_SYNC(7);



	/* OS Lock blocking hardware-breakpoint */

	reset_debug_state();

	enable_os_lock();

	install_hw_bp(PC(hw_bp2));

	install_hw_bp(bpn, PC(hw_bp2));

	hw_bp_addr = 0;

	asm volatile("hw_bp2: nop");

	GUEST_ASSERT_EQ(hw_bp_addr, 0);



	GUEST_SYNC(8);



	/* OS Lock blocking watchpoint */

	reset_debug_state();

	enable_os_lock();

	write_data = '\0';

	wp_data_addr = 0;

	install_wp(PC(write_data));

	install_wp(wpn, PC(write_data));

	write_data = 'x';

	GUEST_ASSERT_EQ(write_data, 'x');

	GUEST_ASSERT_EQ(wp_data_addr, 0);



	GUEST_SYNC(9);



	/* OS Lock blocking single-step */

	reset_debug_state();

	enable_os_lock();
@@ -205,6 +320,27 @@ static void guest_code(void) 
		     : : : "x0");

	GUEST_ASSERT_EQ(ss_addr[0], 0);



	/* Linked hardware-breakpoint */

	hw_bp_addr = 0;

	reset_debug_state();

	install_hw_bp_ctx(bpn, ctx_bpn, PC(hw_bp_ctx), ctx);

	/* Set context id */

	write_sysreg(ctx, contextidr_el1);

	isb();

	asm volatile("hw_bp_ctx: nop");

	write_sysreg(0, contextidr_el1);

	GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp_ctx));



	/* Linked watchpoint */

	reset_debug_state();

	install_wp_ctx(wpn, ctx_bpn, PC(write_data), ctx);

	/* Set context id */

	write_sysreg(ctx, contextidr_el1);

	isb();

	write_data = 'x';

	GUEST_ASSERT_EQ(write_data, 'x');

	GUEST_ASSERT_EQ(wp_data_addr, PC(write_data));



	GUEST_DONE();

}
@@ -279,20 +415,16 @@ static void guest_code_ss(int test_cnt) 
	GUEST_DONE();

}



static int debug_version(struct kvm_vcpu *vcpu)

static int debug_version(uint64_t id_aa64dfr0)

{

	uint64_t id_aa64dfr0;



	vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &id_aa64dfr0);

	return id_aa64dfr0 & 0xf;

	return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), id_aa64dfr0);

}



static void test_guest_debug_exceptions(void)

static void test_guest_debug_exceptions(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn)

{

	struct kvm_vcpu *vcpu;

	struct kvm_vm *vm;

	struct ucall uc;

	int stage;



	vm = vm_create_with_one_vcpu(&vcpu, guest_code);

	ucall_init(vm, NULL);
@@ -311,15 +443,12 @@ static void test_guest_debug_exceptions(void) 
	vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,

				ESR_EC_SVC64, guest_svc_handler);



	for (stage = 0; stage < 11; stage++) {

		vcpu_run(vcpu);

	/* Specify bpn/wpn/ctx_bpn to be tested */

	vcpu_args_set(vcpu, 3, bpn, wpn, ctx_bpn);

	pr_debug("Use bpn#%d, wpn#%d and ctx_bpn#%d\n", bpn, wpn, ctx_bpn);



	vcpu_run(vcpu);

	switch (get_ucall(vcpu, &uc)) {

		case UCALL_SYNC:

			TEST_ASSERT(uc.args[1] == stage,

				"Stage %d: Unexpected sync ucall, got %lx",

				stage, (ulong)uc.args[1]);

			break;

	case UCALL_ABORT:

		REPORT_GUEST_ASSERT_2(uc, "values: %#lx, %#lx");

		break;
@@ -328,7 +457,6 @@ static void test_guest_debug_exceptions(void) 
	default:

		TEST_FAIL("Unknown ucall %lu", uc.cmd);

	}

	}



done:

	kvm_vm_free(vm);
@@ -400,6 +528,43 @@ void test_single_step_from_userspace(int test_cnt) 
	kvm_vm_free(vm);

}



/*

 * Run debug testing using the various breakpoint#, watchpoint# and

 * context-aware breakpoint# with the given ID_AA64DFR0_EL1 configuration.

 */

void test_guest_debug_exceptions_all(uint64_t aa64dfr0)

{

	uint8_t brp_num, wrp_num, ctx_brp_num, normal_brp_num, ctx_brp_base;

	int b, w, c;



	/* Number of breakpoints */

	brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS), aa64dfr0) + 1;

	__TEST_REQUIRE(brp_num >= 2, "At least two breakpoints are required");



	/* Number of watchpoints */

	wrp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS), aa64dfr0) + 1;



	/* Number of context aware breakpoints */

	ctx_brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_CTX_CMPS), aa64dfr0) + 1;



	pr_debug("%s brp_num:%d, wrp_num:%d, ctx_brp_num:%d\n", __func__,

		 brp_num, wrp_num, ctx_brp_num);



	/* Number of normal (non-context aware) breakpoints */

	normal_brp_num = brp_num - ctx_brp_num;



	/* Lowest context aware breakpoint number */

	ctx_brp_base = normal_brp_num;



	/* Run tests with all supported breakpoints/watchpoints */

	for (c = ctx_brp_base; c < ctx_brp_base + ctx_brp_num; c++) {

		for (b = 0; b < normal_brp_num; b++) {

			for (w = 0; w < wrp_num; w++)

				test_guest_debug_exceptions(b, w, c);

		}

	}

}



static void help(char *name)

{

	puts("");
@@ -414,9 +579,11 @@ int main(int argc, char *argv[]) 
	struct kvm_vm *vm;

	int opt;

	int ss_iteration = 10000;

	uint64_t aa64dfr0;



	vm = vm_create_with_one_vcpu(&vcpu, guest_code);

	__TEST_REQUIRE(debug_version(vcpu) >= 6,

	vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &aa64dfr0);

	__TEST_REQUIRE(debug_version(aa64dfr0) >= 6,

		       "Armv8 debug architecture not supported.");

	kvm_vm_free(vm);
@@ -432,7 +599,7 @@ int main(int argc, char *argv[]) 
		}

	}



	test_guest_debug_exceptions();

	test_guest_debug_exceptions_all(aa64dfr0);

	test_single_step_from_userspace(ss_iteration);



	return 0;

tools/testing/selftests/kvm/lib/aarch64/processor.c

+4 −3
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include "guest_modes.h"

#include "kvm_util.h"

#include "processor.h"

#include <linux/bitfield.h>



#define DEFAULT_ARM64_GUEST_STACK_VADDR_MIN	0xac0000
@@ -486,9 +487,9 @@ void aarch64_get_supported_page_sizes(uint32_t ipa, 
	err = ioctl(vcpu_fd, KVM_GET_ONE_REG, &reg);

	TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd));



	*ps4k = ((val >> 28) & 0xf) != 0xf;

	*ps64k = ((val >> 24) & 0xf) == 0;

	*ps16k = ((val >> 20) & 0xf) != 0;

	*ps4k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN4), val) != 0xf;

	*ps64k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN64), val) == 0;

	*ps16k = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN16), val) != 0;



	close(vcpu_fd);

	close(vm_fd);