Commit 02f1e17c authored by Dmitry Rokosov's avatar Dmitry Rokosov Committed by Jerome Brunet
Browse files

clk: meson: make pll rst bit as optional 



Compared with the previous SoCs, self-adaption current module
is newly added for A1, and there is no reset parameter except the
fixed pll. Since we use clk-pll generic driver for A1 pll
implementation, rst bit should be optional to support new behavior.

Signed-off-by: default avatarJian Hu <jian.hu@amlogic.com>
Acked-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarDmitry Rokosov <ddrokosov@sberdevices.ru>
Link: https://lore.kernel.org/r/20230523135351.19133-2-ddrokosov@sberdevices.ru


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 98872da6

drivers/clk/meson/clk-pll.c

+17 −7
Original line number Diff line number Diff line
@@ -295,9 +295,13 @@ static int meson_clk_pll_init(struct clk_hw *hw) 
	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);



	if (pll->init_count) {

		if (MESON_PARM_APPLICABLE(&pll->rst))

			meson_parm_write(clk->map, &pll->rst, 1);



		regmap_multi_reg_write(clk->map, pll->init_regs,

				       pll->init_count);



		if (MESON_PARM_APPLICABLE(&pll->rst))

			meson_parm_write(clk->map, &pll->rst, 0);

	}
@@ -309,8 +313,11 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) 
	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);



	if (meson_parm_read(clk->map, &pll->rst) ||

	    !meson_parm_read(clk->map, &pll->en) ||

	if (MESON_PARM_APPLICABLE(&pll->rst) &&

	    meson_parm_read(clk->map, &pll->rst))

		return 0;



	if (!meson_parm_read(clk->map, &pll->en) ||

	    !meson_parm_read(clk->map, &pll->l))

		return 0;
@@ -341,12 +348,14 @@ static int meson_clk_pll_enable(struct clk_hw *hw) 
		return 0;



	/* Make sure the pll is in reset */

	if (MESON_PARM_APPLICABLE(&pll->rst))

		meson_parm_write(clk->map, &pll->rst, 1);



	/* Enable the pll */

	meson_parm_write(clk->map, &pll->en, 1);



	/* Take the pll out reset */

	if (MESON_PARM_APPLICABLE(&pll->rst))

		meson_parm_write(clk->map, &pll->rst, 0);



	if (meson_clk_pll_wait_lock(hw))
@@ -361,6 +370,7 @@ static void meson_clk_pll_disable(struct clk_hw *hw) 
	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);



	/* Put the pll is in reset */

	if (MESON_PARM_APPLICABLE(&pll->rst))

		meson_parm_write(clk->map, &pll->rst, 1);



	/* Disable the pll */