Commit 02dca8c9 authored by Vinod Koul's avatar Vinod Koul
Browse files

phy: qcom: remove ufs qmp phy driver 



The UFS specific QMP PHY driver started off supporting the 14nm and
20nm hardware. With the 20nm support marked broken for a long time and
the 14nm support added to the common QMP PHY, this driver has not been
used in a while. So delete it

Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200629145452.123035-1-vkoul@kernel.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 1c59c2d9

drivers/phy/qualcomm/Kconfig

+0 −24
Original line number Diff line number Diff line
@@ -59,30 +59,6 @@ config PHY_QCOM_QUSB2 
	  PHY which is usually paired with either the ChipIdea or Synopsys DWC3

	  USB IPs on MSM SOCs.



config PHY_QCOM_UFS

	tristate "Qualcomm UFS PHY driver"

	depends on OF && ARCH_QCOM

	select GENERIC_PHY

	help

	  Support for UFS PHY on QCOM chipsets.



if PHY_QCOM_UFS



config PHY_QCOM_UFS_14NM

	tristate

	default PHY_QCOM_UFS

	help

	  Support for 14nm UFS QMP phy present on QCOM chipsets.



config PHY_QCOM_UFS_20NM

	tristate

	default PHY_QCOM_UFS

	depends on BROKEN

	help

	  Support for 20nm UFS QMP phy present on QCOM chipsets.



endif



config PHY_QCOM_USB_HS

	tristate "Qualcomm USB HS PHY module"

	depends on USB_ULPI_BUS

drivers/phy/qualcomm/Makefile

+0 −3
Original line number Diff line number Diff line
@@ -6,9 +6,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o 
obj-$(CONFIG_PHY_QCOM_PCIE2)		+= phy-qcom-pcie2.o

obj-$(CONFIG_PHY_QCOM_QMP)		+= phy-qcom-qmp.o

obj-$(CONFIG_PHY_QCOM_QUSB2)		+= phy-qcom-qusb2.o

obj-$(CONFIG_PHY_QCOM_UFS)		+= phy-qcom-ufs.o

obj-$(CONFIG_PHY_QCOM_UFS_14NM)		+= phy-qcom-ufs-qmp-14nm.o

obj-$(CONFIG_PHY_QCOM_UFS_20NM)		+= phy-qcom-ufs-qmp-20nm.o

obj-$(CONFIG_PHY_QCOM_USB_HS) 		+= phy-qcom-usb-hs.o

obj-$(CONFIG_PHY_QCOM_USB_HSIC) 	+= phy-qcom-usb-hsic.o

obj-$(CONFIG_PHY_QCOM_USB_HS_28NM)	+= phy-qcom-usb-hs-28nm.o

drivers/phy/qualcomm/phy-qcom-ufs-i.h

deleted100644 → 0
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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.

 */



#ifndef UFS_QCOM_PHY_I_H_

#define UFS_QCOM_PHY_I_H_



#include <linux/module.h>

#include <linux/clk.h>

#include <linux/phy/phy.h>

#include <linux/regulator/consumer.h>

#include <linux/reset.h>

#include <linux/slab.h>

#include <linux/platform_device.h>

#include <linux/io.h>

#include <linux/delay.h>

#include <linux/iopoll.h>



#define UFS_QCOM_PHY_CAL_ENTRY(reg, val)	\

	{				\

		.reg_offset = reg,	\

		.cfg_value = val,	\

	}



#define UFS_QCOM_PHY_NAME_LEN	30



enum {

	MASK_SERDES_START       = 0x1,

	MASK_PCS_READY          = 0x1,

};



enum {

	OFFSET_SERDES_START     = 0x0,

};



struct ufs_qcom_phy_stored_attributes {

	u32 att;

	u32 value;

};





struct ufs_qcom_phy_calibration {

	u32 reg_offset;

	u32 cfg_value;

};



struct ufs_qcom_phy_vreg {

	const char *name;

	struct regulator *reg;

	int max_uA;

	int min_uV;

	int max_uV;

	bool enabled;

};



struct ufs_qcom_phy {

	struct list_head list;

	struct device *dev;

	void __iomem *mmio;

	void __iomem *dev_ref_clk_ctrl_mmio;

	struct clk *tx_iface_clk;

	struct clk *rx_iface_clk;

	bool is_iface_clk_enabled;

	struct clk *ref_clk_src;

	struct clk *ref_clk_parent;

	struct clk *ref_clk;

	bool is_ref_clk_enabled;

	bool is_dev_ref_clk_enabled;

	struct ufs_qcom_phy_vreg vdda_pll;

	struct ufs_qcom_phy_vreg vdda_phy;

	struct ufs_qcom_phy_vreg vddp_ref_clk;

	unsigned int quirks;



	/*

	* If UFS link is put into Hibern8 and if UFS PHY analog hardware is

	* power collapsed (by clearing UFS_PHY_POWER_DOWN_CONTROL), Hibern8

	* exit might fail even after powering on UFS PHY analog hardware.

	* Enabling this quirk will help to solve above issue by doing

	* custom PHY settings just before PHY analog power collapse.

	*/

	#define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE	BIT(0)



	u8 host_ctrl_rev_major;

	u16 host_ctrl_rev_minor;

	u16 host_ctrl_rev_step;



	char name[UFS_QCOM_PHY_NAME_LEN];

	struct ufs_qcom_phy_calibration *cached_regs;

	int cached_regs_table_size;

	struct ufs_qcom_phy_specific_ops *phy_spec_ops;



	enum phy_mode mode;

	struct reset_control *ufs_reset;

};



/**

 * struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a

 * specific implementation per phy. Each UFS phy, should implement

 * those functions according to its spec and requirements

 * @start_serdes: pointer to a function that starts the serdes

 * @is_physical_coding_sublayer_ready: pointer to a function that

 * checks pcs readiness. returns 0 for success and non-zero for error.

 * @set_tx_lane_enable: pointer to a function that enable tx lanes

 * @power_control: pointer to a function that controls analog rail of phy

 * and writes to QSERDES_RX_SIGDET_CNTRL attribute

 */

struct ufs_qcom_phy_specific_ops {

	int (*calibrate)(struct ufs_qcom_phy *ufs_qcom_phy, bool is_rate_B);

	void (*start_serdes)(struct ufs_qcom_phy *phy);

	int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy);

	void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val);

	void (*power_control)(struct ufs_qcom_phy *phy, bool val);

};



struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy);

int ufs_qcom_phy_power_on(struct phy *generic_phy);

int ufs_qcom_phy_power_off(struct phy *generic_phy);

int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common);

int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common);

int ufs_qcom_phy_remove(struct phy *generic_phy,

		       struct ufs_qcom_phy *ufs_qcom_phy);

struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,

			struct ufs_qcom_phy *common_cfg,

			const struct phy_ops *ufs_qcom_phy_gen_ops,

			struct ufs_qcom_phy_specific_ops *phy_spec_ops);

int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,

			struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,

			struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,

			bool is_rate_B);

#endif

drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c

deleted100644 → 0
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Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.

 */



#include "phy-qcom-ufs-qmp-14nm.h"



#define UFS_PHY_NAME "ufs_phy_qmp_14nm"

#define UFS_PHY_VDDA_PHY_UV	(925000)



static

int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,

					bool is_rate_B)

{

	int tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);

	int tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);

	int err;



	err = ufs_qcom_phy_calibrate(ufs_qcom_phy, phy_cal_table_rate_A,

		tbl_size_A, phy_cal_table_rate_B, tbl_size_B, is_rate_B);



	if (err)

		dev_err(ufs_qcom_phy->dev,

			"%s: ufs_qcom_phy_calibrate() failed %d\n",

			__func__, err);

	return err;

}



static

void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)

{

	phy_common->quirks =

		UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;

}



static

int ufs_qcom_phy_qmp_14nm_set_mode(struct phy *generic_phy,

				   enum phy_mode mode, int submode)

{

	struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);



	phy_common->mode = PHY_MODE_INVALID;



	if (mode > 0)

		phy_common->mode = mode;



	return 0;

}



static

void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val)

{

	writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);

	/*

	 * Before any transactions involving PHY, ensure PHY knows

	 * that it's analog rail is powered ON (or OFF).

	 */

	mb();

}



static inline

void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)

{

	/*

	 * 14nm PHY does not have TX_LANE_ENABLE register.

	 * Implement this function so as not to propagate error to caller.

	 */

}



static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy)

{

	u32 tmp;



	tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);

	tmp &= ~MASK_SERDES_START;

	tmp |= (1 << OFFSET_SERDES_START);

	writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);

	/* Ensure register value is committed */

	mb();

}



static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)

{

	int err = 0;

	u32 val;



	err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,

		val, (val & MASK_PCS_READY), 10, 1000000);

	if (err)

		dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",

			__func__, err);

	return err;

}



static const struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {

	.power_on	= ufs_qcom_phy_power_on,

	.power_off	= ufs_qcom_phy_power_off,

	.set_mode	= ufs_qcom_phy_qmp_14nm_set_mode,

	.owner		= THIS_MODULE,

};



static struct ufs_qcom_phy_specific_ops phy_14nm_ops = {

	.calibrate		= ufs_qcom_phy_qmp_14nm_phy_calibrate,

	.start_serdes		= ufs_qcom_phy_qmp_14nm_start_serdes,

	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,

	.set_tx_lane_enable	= ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,

	.power_control		= ufs_qcom_phy_qmp_14nm_power_control,

};



static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct phy *generic_phy;

	struct ufs_qcom_phy_qmp_14nm *phy;

	struct ufs_qcom_phy *phy_common;

	int err = 0;



	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);

	if (!phy) {

		err = -ENOMEM;

		goto out;

	}

	phy_common = &phy->common_cfg;



	generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,

				&ufs_qcom_phy_qmp_14nm_phy_ops, &phy_14nm_ops);



	if (!generic_phy) {

		err = -EIO;

		goto out;

	}



	err = ufs_qcom_phy_init_clks(phy_common);

	if (err)

		goto out;



	err = ufs_qcom_phy_init_vregulators(phy_common);

	if (err)

		goto out;



	phy_common->vdda_phy.max_uV = UFS_PHY_VDDA_PHY_UV;

	phy_common->vdda_phy.min_uV = UFS_PHY_VDDA_PHY_UV;



	ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common);



	phy_set_drvdata(generic_phy, phy);



	strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));



out:

	return err;

}



static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match[] = {

	{.compatible = "qcom,ufs-phy-qmp-14nm"},

	{.compatible = "qcom,msm8996-ufs-phy-qmp-14nm"},

	{},

};

MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_14nm_of_match);



static struct platform_driver ufs_qcom_phy_qmp_14nm_driver = {

	.probe = ufs_qcom_phy_qmp_14nm_probe,

	.driver = {

		.of_match_table = ufs_qcom_phy_qmp_14nm_of_match,

		.name = "ufs_qcom_phy_qmp_14nm",

	},

};



module_platform_driver(ufs_qcom_phy_qmp_14nm_driver);



MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");

MODULE_LICENSE("GPL v2");

drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.

 */



#ifndef UFS_QCOM_PHY_QMP_14NM_H_

#define UFS_QCOM_PHY_QMP_14NM_H_



#include "phy-qcom-ufs-i.h"



/* QCOM UFS PHY control registers */

#define COM_OFF(x)	(0x000 + x)

#define PHY_OFF(x)	(0xC00 + x)

#define TX_OFF(n, x)	(0x400 + (0x400 * n) + x)

#define RX_OFF(n, x)	(0x600 + (0x400 * n) + x)



/* UFS PHY QSERDES COM registers */

#define QSERDES_COM_BG_TIMER			COM_OFF(0x0C)

#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN		COM_OFF(0x34)

#define QSERDES_COM_SYS_CLK_CTRL		COM_OFF(0x3C)

#define QSERDES_COM_LOCK_CMP1_MODE0		COM_OFF(0x4C)

#define QSERDES_COM_LOCK_CMP2_MODE0		COM_OFF(0x50)

#define QSERDES_COM_LOCK_CMP3_MODE0		COM_OFF(0x54)

#define QSERDES_COM_LOCK_CMP1_MODE1		COM_OFF(0x58)

#define QSERDES_COM_LOCK_CMP2_MODE1		COM_OFF(0x5C)

#define QSERDES_COM_LOCK_CMP3_MODE1		COM_OFF(0x60)

#define QSERDES_COM_CP_CTRL_MODE0		COM_OFF(0x78)

#define QSERDES_COM_CP_CTRL_MODE1		COM_OFF(0x7C)

#define QSERDES_COM_PLL_RCTRL_MODE0		COM_OFF(0x84)

#define QSERDES_COM_PLL_RCTRL_MODE1		COM_OFF(0x88)

#define QSERDES_COM_PLL_CCTRL_MODE0		COM_OFF(0x90)

#define QSERDES_COM_PLL_CCTRL_MODE1		COM_OFF(0x94)

#define QSERDES_COM_SYSCLK_EN_SEL		COM_OFF(0xAC)

#define QSERDES_COM_RESETSM_CNTRL		COM_OFF(0xB4)

#define QSERDES_COM_LOCK_CMP_EN			COM_OFF(0xC8)

#define QSERDES_COM_LOCK_CMP_CFG		COM_OFF(0xCC)

#define QSERDES_COM_DEC_START_MODE0		COM_OFF(0xD0)

#define QSERDES_COM_DEC_START_MODE1		COM_OFF(0xD4)

#define QSERDES_COM_DIV_FRAC_START1_MODE0	COM_OFF(0xDC)

#define QSERDES_COM_DIV_FRAC_START2_MODE0	COM_OFF(0xE0)

#define QSERDES_COM_DIV_FRAC_START3_MODE0	COM_OFF(0xE4)

#define QSERDES_COM_DIV_FRAC_START1_MODE1	COM_OFF(0xE8)

#define QSERDES_COM_DIV_FRAC_START2_MODE1	COM_OFF(0xEC)

#define QSERDES_COM_DIV_FRAC_START3_MODE1	COM_OFF(0xF0)

#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0	COM_OFF(0x108)

#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0	COM_OFF(0x10C)

#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1	COM_OFF(0x110)

#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1	COM_OFF(0x114)

#define QSERDES_COM_VCO_TUNE_CTRL		COM_OFF(0x124)

#define QSERDES_COM_VCO_TUNE_MAP		COM_OFF(0x128)

#define QSERDES_COM_VCO_TUNE1_MODE0		COM_OFF(0x12C)

#define QSERDES_COM_VCO_TUNE2_MODE0		COM_OFF(0x130)

#define QSERDES_COM_VCO_TUNE1_MODE1		COM_OFF(0x134)

#define QSERDES_COM_VCO_TUNE2_MODE1		COM_OFF(0x138)

#define QSERDES_COM_VCO_TUNE_TIMER1		COM_OFF(0x144)

#define QSERDES_COM_VCO_TUNE_TIMER2		COM_OFF(0x148)

#define QSERDES_COM_CLK_SELECT			COM_OFF(0x174)

#define QSERDES_COM_HSCLK_SEL			COM_OFF(0x178)

#define QSERDES_COM_CORECLK_DIV			COM_OFF(0x184)

#define QSERDES_COM_CORE_CLK_EN			COM_OFF(0x18C)

#define QSERDES_COM_CMN_CONFIG			COM_OFF(0x194)

#define QSERDES_COM_SVS_MODE_CLK_SEL		COM_OFF(0x19C)

#define QSERDES_COM_CORECLK_DIV_MODE1		COM_OFF(0x1BC)



/* UFS PHY registers */

#define UFS_PHY_PHY_START			PHY_OFF(0x00)

#define UFS_PHY_POWER_DOWN_CONTROL		PHY_OFF(0x04)

#define UFS_PHY_PCS_READY_STATUS		PHY_OFF(0x168)



/* UFS PHY TX registers */

#define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN	TX_OFF(0, 0x68)

#define QSERDES_TX_LANE_MODE				TX_OFF(0, 0x94)



/* UFS PHY RX registers */

#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	RX_OFF(0, 0x40)

#define QSERDES_RX_RX_TERM_BW			RX_OFF(0, 0x90)

#define QSERDES_RX_RX_EQ_GAIN1_LSB		RX_OFF(0, 0xC4)

#define QSERDES_RX_RX_EQ_GAIN1_MSB		RX_OFF(0, 0xC8)

#define QSERDES_RX_RX_EQ_GAIN2_LSB		RX_OFF(0, 0xCC)

#define QSERDES_RX_RX_EQ_GAIN2_MSB		RX_OFF(0, 0xD0)

#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	RX_OFF(0, 0xD8)

#define QSERDES_RX_SIGDET_CNTRL			RX_OFF(0, 0x114)

#define QSERDES_RX_SIGDET_LVL			RX_OFF(0, 0x118)

#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL	RX_OFF(0, 0x11C)

#define QSERDES_RX_RX_INTERFACE_MODE		RX_OFF(0, 0x12C)



/*

 * This structure represents the 14nm specific phy.

 * common_cfg MUST remain the first field in this structure

 * in case extra fields are added. This way, when calling

 * get_ufs_qcom_phy() of generic phy, we can extract the

 * common phy structure (struct ufs_qcom_phy) out of it

 * regardless of the relevant specific phy.

 */

struct ufs_qcom_phy_qmp_14nm {

	struct ufs_qcom_phy common_cfg;

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x05),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x10),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x14),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),



	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x02),



	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x54),

};



#endif