Commit 02d8091b authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: msm8994: Add a proper CPU map 



Add a proper CPU map to enable the use of all 8 cores.

Signed-off-by: default avatarKonrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200623224813.297077-4-konradybcio@gmail.com


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent b0ad598f

arch/arm64/boot/dts/qcom/msm8994.dtsi

+102 −10
Original line number Diff line number Diff line
@@ -28,26 +28,118 @@ 
	};



	cpus {

		#address-cells = <1>;

		#address-cells = <2>;

		#size-cells = <0>;

		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

				compatible = "cache";

				cache-level = <2>;

			};

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x1>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};



		CPU0: cpu@0 {

		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			reg = <0x0 0x2>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x3>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};



		CPU4: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

				compatible = "cache";

				cache-level = <2>;

			};

		};



		CPU5: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x101>;

			enable-method = "psci";

			next-level-cache = <&L2_1>;

		};



		CPU6: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x101>;

			enable-method = "psci";

			next-level-cache = <&L2_1>;

		};



		CPU7: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x101>;

			enable-method = "psci";

			next-level-cache = <&L2_1>;

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

				};



				core1 {

					cpu = <&CPU1>;

				};



				core2 {

					cpu = <&CPU2>;

				};



				core3 {

					cpu = <&CPU3>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&CPU4>;

				};



				core1 {

					cpu = <&CPU5>;

				};



				core2 {

					cpu = <&CPU6>;

				};



				core3 {

					cpu = <&CPU7>;

				};

			};

		};

	};



	memory {