Commit 02c55535 authored by Rohit Agarwal's avatar Rohit Agarwal Committed by Bjorn Andersson
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ARM: dts: qcom: sdx65: Add support for A7 PLL clock 



On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: default avatarRohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com
parent c20aa951

arch/arm/boot/dts/qcom-sdx65.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -121,6 +121,14 @@ 
			      <0x17802000 0x1000>;

		};



		a7pll: clock@17808000 {

			compatible = "qcom,sdx55-a7pll";

			reg = <0x17808000 0x1000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "bi_tcxo";

			#clock-cells = <0>;

		};



		timer@17820000 {

			#address-cells = <1>;

			#size-cells = <1>;